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ASE to build new packaging facility in Kaohsiung Taipei Times reports that ASE, the world’s biggest chip assembly and testing service provider, said it is investing $578.6M to build a new advanced chip packaging facility in Kaohsiung to cope with fast-growing demand from artificial intelligence (AI), high-performance-computing (HPC) and automotive...
More than a few years ago, somewhere around 28nm, my working group was discussing the potential demise of “Moore’s Law”. The industry and international technology roadmap committee were struggling with hi-k metal gates, strain, FinFETs, and of course how lithography could keep shrinking. The designing and manufacturing of a system...
In a recent IMAPS webinar, John Park (Figure 1), product management director of Cadence Design Systems, gave a tutorial entitled “This Is Not Your Father’s Advanced Semiconductor Packaging…an EDA Perspective”. Herb Reiter reviewed it here. While a lot of the technical detail that he shared was probably beyond the older...
At IWLPC 2019, the fan-out panel-level packaging (PLP) debate continued in another of Jan Vardaman’s famous lively panel discussions, which was co-moderated by PLP technology expert, Tanja Braun, Fraunhofer IZM. Panelists were John Hunt, ASE; Joseph Dang, AT&S; Keith Best, Rudolph Technologies; Tim Olson, Deca Technologies. Fan-out PLP (FO PLP)...
The semiconductor industry is at a turning point. The slowdown in CMOS scaling, coupled with escalating costs, has prompted the industry to rely on integrated circuit (IC) packaging to extend the benefits of the More-than-Moore era. Thus, the advanced packaging industry has entered its most successful period, boosted by widespread...
Sitting in the bus on the way back from Grenoble to Airport Lyon, I am reflecting the last two days during which we honored Gilles Poupon, the Advanced Packaging “Pope” of CEA Leti. Upon his retirement at the end of November 2017, somehow an era ends. I have known Gilles...
TechSearch International Analysis Predicts Growth for Fan-in and FO-WLP TechSearch International predicts strong market growth for fan-in wafer level packages (WLPs) and fan-out WLP (FO-WLP). Driven by demand for thin, low-profile packages in smartphones, tablets, and wearable devices such as smart watches, fitness bands, and virtual reality headsets, fan-in WLPs...
You might recall that a few year’s back (October 2013, to be precise), 3D InCites’ regular blogger, Paul Werbaneth, had the opportunity to interview Dongkai Shangguan, then CEO of the National Center for Advanced Packaging (NCAP) in Wuxi, China, which he helped found along with nine investors. They talked about...
Last year, I did an analysis that included the topic of wafer-to-wafer bonding. Specifically, it was a comparison of the three variations available when stacking wafers and/or die—wafer-to-wafer (W2W), die-to-wafer (D2W), and die-to-die (D2D). The goal of that project was to build cost models for W2W and D2W (with the...
New NSX Metrology Series includes application-specific configurations to address unique metrology requirements for wafer level packaging, 2.5D and 3DIC Rudolph Technologies, Inc. (NASDAQ: RTEC), a leading provider of process characterization, photolithography equipment and software for the semiconductor, FPD, LED and solar industries, today released three new application-specific configurations of its...
