Figure 1: Cadence’ John Park presented an EDA perspective of advanced packaging.

In a recent IMAPS webinar, John Park (Figure 1), product management director of Cadence Design Systems, gave a tutorial entitled “This Is Not Your Father’s Advanced Semiconductor Packaging…an EDA Perspective”. Herb Reiter reviewed it here.

While a lot of the technical detail that he shared was probably beyond the older generation of packaging technologists, the overall message that it relayed was accurate and worthy of examining further. A more detailed look at where we were 30 years ago with microelectronic packaging might better set the stage for John’s message, a least for the younger practitioners in our field.

Microelectronic Packaging in the Old Days

First, let’s take a look at where the old-timers (your figurative fathers) came from. Just to give some personal perspective I entered the field at the behest of Dow Chemical’s Boston R&D center, in the early 1980s, with a Ph.D. in Chemistry (focus on organometallics) and access to the early electronic giants like Digital Equipment that were all located around Rt 128 outside Boston. Remember, before there was Silicon Valley in San Jose there was Rt 128 around Boston.

My charter was to live with the electronics industry and learn what new materials they would need as they developed leading-edge processes. By 1986 I had moved to NC and was receiving training from the likes of Arne Reisman who had taken early retirement from IBM to build a chip line in Research Triangle Park called Microelectronics Center of NC (MCNC). However, his 1µm IC line was soon obsolete and they astutely moved their focus from chips to packaging in order to stay relevant. By 1990 they were developing what is today’s plated bump process (under Govt and IBM funding), were doing redistribution layers (RDL) before anyone else knew what the words meant, and became leaders in thin-film packaging technology under the leadership of another of my mentors Iwona Turlik (later a Sr. Dir. at Motorola). They spun out Unitive as a bumping startup shortly afterward and it was later acquired by Amkor.

I began attending the IEEE Electronics Component Technology Conference (ECTC) and IMAPS conferences in the mid-1980s and began to understand the infrastructure that was/is packaging. Leading-edge packaging back then was all about hybrids and ceramics. What today is the IEEE Electronics Packaging Society (IEEE EPS), back in 1987 was the Components, Hybrids, and Manufacturing Technology (CHMT) society and what today is International Microelectronics Assembly & Packaging Society (IMAPS) was then International Society for Hybrid Microelectronics (ISHM). The substrates were fired ceramics and the conductors were screen-printed pastes that were fired to produce conductor lines that were measured in mils (25um/mil), not microns. Wirebonding had been around for less than a decade and bumping was an obscure process only used by IBM for their mainframe computers. Low-end individual chips, when packaged, were wire bonded to a lead frame and encapsulated in an epoxy concoction called “molding compound”. Basically, all advanced chips were packaged in ceramic packages.

By 1990 surface mounting had begun to replace through-hole mounting, Motorola had just introduced the ball grid array (BGA) at ECTC, but any form of a chip-scale package, let alone stacked chips, was still a dream (Figures 2 & 3).

microelectronic packaging through the years

Figure 2: Microelectronic packaging’s early days.

Figure 3: Timeline of microelectronic packaging technologies.

Basically, packaging was a field composed of mechanical engineers and chemical engineers and chemists, not really electrical engineers and/or chip designers. My observation, back then, was that the front end and the back end actually spoke in different languages and did not read each other’s publications.  The front end, i.e the chip guys, always drove the industry. The packaging was something that needed to be done to protect and test the chips but packaging certainly did not create value or offer any product differentiation vs a competitor. Without question, the packaging community was second class citizens.

With the demise of Moore’s Law (I’m with the group that thinks it happened around 28nm), things have significantly changed. I certainly have used my platform to become a campanologist (bell ringer) for the premise that the importance of packaging has increased to the point where it IS now being used to differentiate products in the market because of the increased performance it can bring when done correctly.

In fact, it has become so important that the front enders, those who used to throw the chip over the wall and say “package it” now understand that proper use of packaging requires “co-design” i.e matching the proper IC technology with the proper packaging technology. This is depicted by John Park in Figure 4:

microelectronic packaging timeline

FIgure 4: The timeline for chip/package co-design urgency (Source: John Park, Cadence)

The Design Community Heeds the Call

The design community, which also used to ignore packaging because that’s not where the money was being spent, has now stood up and is paying attention. In fact, Park, indicating that “heterogeneously integrated” system-in-package (SiP) (here we go with the buzz words again) will be leveraged to design the next-generation electronic products stated flat out stated, “SiP will replace SoC”.

He actually showed a slide touting chiplets and IC disintegration as the new leading edge and saying that all Cadence EDA tools will be usable with new chiplet based packaging solutions (Figure 5).

Figure 5:Advantages of chiplet technology vs. SoC design. (Source: John Park, Cadence Design Systems)

As advanced packaging design features approach a micron (where we were 30+ years ago on Arnie Reisman’s MCNC IC line) packaging must be codesigned with all the EDA tools normally used to layout advanced chips.

Another trend that Cadence has observed is one that IFTLE has also been pushing for the last few years, i.e. that foundries are taking over the advanced packaging space. With the likes of TSMC, Samsung, and Intel delivering most of the new packaging solutions lately, is it really that strange that Cadence and the other EDA players have entered the field? Park’s message was basically that all the Cadence design tools were now packaging friendly and that most of the new packaging technologies could be developed in conjunction with the new chips (co-design). This is great for our technology advancement and for our community.

The IFTLE message to old-time packaging engineers is “better get on board and start learning about these design tools because they are quickly becoming a part of your future!

For all the latest on Advanced Packaging stay linked to IFTLE. ……………………………..

Phil Garrou

Dr. Philip Garrou is a subject matter expert for DARPA and runs his consulting company…

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