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Building a Chiplet Ecosystem

The semiconductor industry’s decades-long adherence to Moore’s Law doctrine of doubling transistor counts on monolithic devices every 18 – 24 months has been amazingly successful. It’s now possible to integrate tens of billions of transistors onto a monolithic die whose area may be hundreds of square millimeters. The resulting chips...

IFTLE 517: Chiplet Standardization Closer than ever with UCIe

The impressive industry grouping of ASE, AMD, ARM, Google, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC in early March announced the formation of an industry consortium that will establish a die-to-die interconnect standard and foster an open chiplet ecosystem. Those of you who follow IFTLE know this is exactly what...

The Advantages of Outsourced Test Services

The business model in today’s competitive world of commerce has shifted over recent years to “services.” Companies like Microsoft, Amazon, and Google are prime success stories that have advanced the industry with business-enabling services. These economic productivity improvement services allow their customers to focus on product architecture, design, and quick...

Is the IoT Headed for the Trough of Disillusionment?

No SEMI Summit would be complete without a lively panel discussion that puts industry experts in the hot seat. The panel at the first SEMI European MEMS Summit, titled IoT Beyond the Hype: What are the Hard Facts?, didn’t disappoint for much as what was discussed, as for what was glossed...

PDN Design, Target Impedance and Path Finding for IC, Package, and PCB

I am fortunate to work with Prof. Madhavan Swaminathan, Founder, CTO, E-System Design, and inventor of our algorithms. Long ago, as an undergraduate engineering student at University of Illinois focused on integrated circuit (IC) design, I enrolled in the required ElectroMagnetics (EM) course to discover it was all about large...

SEMICON West Keynote Panel: Semiconductor Manufacturing is a Team Sport

I almost didn’t attend the keynote panel titled, Scaling the Walls of Sub 14nm Manufacturing, at SEMICON West last week, because in my experience as a blogger/journalist focused on advanced packaging, interposer integration and 3D ICs, discussions on scaling rarely talk about packaging. In fact, up until now, it’s been...

BiTS Workshop Rebrands to Keep Pace with Packaging Evolution

The Burn‐in & Test Socket Workshop (BiTS Workshop) announced today that it is changing its name to The Burn‐in & Test Strategies Workshop (BiTS Workshop). The rebrand, which features an updated logo, is reflected in all of BiTS collateral material and the website for the 2012 BiTS Workshop that takes...

A Little Disruption can be Good for You!

Two weeks ago, wearing my Chip Scale Review Sr. technical editor hat, I attended (along with 11 other journalists) an exclusive press conference launching a new electronic interconnect company, Deca Technologies, which claims to have developed disruptive manufacturing processes based on its sister company, SunPower’s, solar cell wafer processes, rather...

May Events in 3D

I wish I could be everywhere at once, because there are so many events involving 3D coming up well worth attending. Unfortunately short of cloning myself, which I don’t think the world is ready for, there’s no way for me to cover everything. So instead, I’ve come up with an...

Live, from Dobson Ranch, it’s MEPTEC’s Southwest Luncheon

While I’m clearly a huge believer of leveraging the Internet for interactive communication (heck, 3D InCItes was founded on that) I have to admit that there’s still no substitute for human interaction. Attending yesterday’s MEPTEC Southwest Luncheon, featuring Mark Stromberg from Gartner Dataquest, offered more than just an update on...