I wish I could be everywhere at once, because there are so many events involving 3D coming up well worth attending. Unfortunately short of cloning myself, which I don’t think the world is ready for, there’s no way for me to cover everything. So instead, I’ve come up with an alternative plan that I hope will also serve to make this blog more interactive, and encourage an exchange of ideas and information in the 3D space. I’ll list the events here and point out the 3D highlights. If you think you’ll be attending, and have time to contribute a brief review or even just a few comments from whatever event/sessions you attend, please drop me a line at firstname.lastname@example.org.
May 13, Through-Silicon Vias (TSVs): Design and Reliability, Santa Clara, CA
This dinner/presentation, co-sponsored by IEEE Santa Clara Valley CPMT Society Chapter, with Electron Devices Chapter, Reliability Chapter, and Circuits and Systems Chapter features Sergey Savastiouk of ALLVIA, who will address the physical design and reliability issues associated with copper through-silicon vias that have not been fully resolved. I suspect that Savastiouk, considered to be one of the pioneers in TSV and founder of the first TSV foundry, can certainly provide a first-hand perspective of what is yet to be overcome before TSV reaches full market adoption. Harvey Miller of IEEE will guest blog this event. I’m looking forward to reading his review.
May 20 – 22, SEMICON Singapore 2009
Known as the Asian epicentre for test, assembly and packaging, this SEMI-sponsored event has always been the one to focus in the back-end. A review of the symposium line-up turned up two 3D focused presentations; New Packaging Solutions for Wireless: Wafer Level Package 3D Evolution, presented by Xavier Baraton, of ST Microelectronics Pte Ltd; and Approaches and Strategies for TSV, presented by Vish Srinivasan of Applied Materials.
May 27-29, ECTC 2009 – San Diego, CA
In addition to the obvious 3D focused sessions, such as 3D IC integration, TSV, Interconnects for 3D IC integration, and TSV characterization, 3D focused presentations cross over into many of ECTC’s sessions. To name a few, as part of the advanced flip chip packaging session, representatives of STATS ChipPAC will present a paper titled “Three-tier PoP Configuration Utilizing Flip Chip Fan-In PoP Bottom Package”; and as part of the MEMS MEMS, Sensors, and Embedded Packaging Technologies session, representatives of Infineon will present a paper about 3D image sensors using 3D interposers. Even though I plan on attending and covering as much as I can myself, I’d certainly welcome guest blogger contributions for this event.
May 29, 2009 Design Technologies for 3D Integration – CEA-Leti, Grenoble, France
As an extension of their R&D partnership, CEA-Leti and Ecole Polytechnique Fédérale de Lausanne (EPFL), have launched a monthly seminar series for students and professionals to discuss technical issues facing micro- and nanotechnology researchers. This seminar, led by Dr. Vasileios Pavlidis, will take place at Leti, in Grenoble France.
That’s a lot happening for one little month. Since May jumps right into June, and events are happening early, I’ll post June events later this week. – F.v.T