Is Copper Sintering the Key to Advancing Wide Band Gap Semiconductors?
Dec 09, 2025 · By Henkel · 3D In-Depth, Materials
Design View all
A Comprehensive Approach to 3D IC Physical Verification: Tackling DRC, LVS and Beyond
As the industry pushes toward ever-greater levels of semiconductor performance, integration and efficiency, the promise of 3D integrated circuits (3D ICs) stands out as a true game-changer. By stacking dies and embracing heterogeneous integration, 3D ICs make it possible to create compact, power-efficient systems far beyond what can be achieved...
Multi Physics Analysis of 3D Integrated Circuits
3D integration is becoming a valuable alternative to the ongoing, yet challenging, transistor scaling known as Moore’s Law. This is especially true for semiconductor products that are becoming limited by single die designs (e.g., in terms of form factor, size, and technology node). Homogenous 2.5D-IC approaches help bring about the...
Devices View all
How AiP Technology Helps Enable 5G and More
For 5G smartphones and other millimeter-wave (mmWave) applications, antenna integration, either through antenna-in-package (AiP) or antenna-on-package (AoP) technologies, simplifies the challenges associated with designing products that operate at these high frequencies. A variety of AiP/AoP design methodologies provide the required form, fit, and function for these applications and can include...
System-on-Chip Disintegration is Underway
We have known for some time that with scaling coming to an end the industry would need to find another way to continue moving forward. One of the options is known as SoC disintegration, which is when a system-on-chip (SoC) is disintegrated into its functional parts and then connect these...
Latest Posts - Page 29
Taking the “pick” out of pick-and-place
Up until now, although it was possible to manufacture miniscule (e.g. 175µm square) RFID and wireless sensor chips using advanced...Alchimer Introduces AquiVia Deposition Process
Alchimer S.A. announced that its AquiVia deposition process is ready for implementation. AquiVia process can reportedly reduce overall cost...
Bringing Transparency to 3D Integrated Structures – Olympus Confocal IR Microscopy
Metrology is consistently one of the more challenging areas in the semiconductor field. Whether it’s the monitoring of ultra-small...
Inside CEA-Leti’s 3D Toolbox
Grenoble-based research institute CEA-Leti’s progress is fueled by a single mission: create innovation and transfer it to industry. The goal...SUSS MicroTec workshop zeroes in on wafer thinning and handling issues
Last year, it was all about through silicon vias (TSVs), this year, it’s all about everything else needed to...
IMEC and SUSS MicroTec to collaborate on wafer bonding for 3D integration
SUSS MicroTec and IMEC have entered a joint development program to develop permanent bonding, temporary bonding...Trends and challenges for thin wafer processing
Processes addressing the handling of ultra-thin wafers have been a hot topic ever since it became clear that they are...3d is hot at SEMICON West
Given the building momentum around 3D integration schemes and the attention it's getting as the semiconductor bright spot, it's...
At IMAPS 2009, IBM Bradley McCredie gets real about scaling
It looks like it’s time to throw in the towel on scaling. According to Bradley McCredie, Ph.D., IBM fellow and...IWLPC 2009 speakers put 3D up front
Sure, 3D integration and packaging isn’t the only game in the semiconductor industry town, but even at events like last...Alchimer introduces seedless wet deposition; eliminates entire step from TSV stacking
Alchimer S.A.,provider of technology for the deposition of nanometric films used in both semiconductor interconnects and 3D through-silicon vias (TSV),...Jisso International Council 2009: Defining 3D
The Jisso International Council (JIC) successfully completed its 10th annual meeting at the facilities of Minatec in Grenoble, France,...
