Sure, 3D integration and packaging isn’t the only game in the semiconductor industry town, but even at events like last week’s 2009 International Wafer-Level Packaging Conference (IWLPC), which covers the gamut of packaging technologies, 3D topics are the main attraction. Speakers and panelists pointed to 3D solutions at the wafer, package and system levels as elemental to the industry future. All though 3D had a track all to itself, 3D and TSV presentations spilled over into the WLP track – clearly a sign that 3D is becoming ubiquitous.
Bill Bottoms, Ph.D. of NanoNexus and iNemi, perhaps declared the reason for this most succinctly as plenary speaker Friday morning:, “ We’re coming to an era in electronics manufacturing where the only way to achieve what we need is through the 3rd dimension.” He even went so far as to say that the very future of this industry growth relies on the success of 3D integration. And he reminded us that the 3D concept is nothing new. Multiple technologies that exploit the Z-direction are available. “We’ve been doing it for a long time,” he noted, “the question is how do we select the ones that will get us the best functional density at the lowest cost? It’s not going to be wire bond. It’s going to be TSV.” The reasons for this are multiple. Bottoms notes that with TSV, interconnect length is reduced dramatically allowing for faster circuit speed and reduced power consumption.
However, Bottoms also admits that many challenges remain before TSV becomes mainstream. The cost for “drill and fill” needs to be reduced, equipment, process times and yields need to change. He called stress management and area the “density penality.” Reliability also isn’t there yet. “But there’s no fundamental reason why it won’t be at some point.” He notes. “There is work to be done.”
Bottoms talked about the importance of material alternatives as part of this work. He said that the ITRS and MIT’s Microphotonics Center are collaborating on the implementation of a 3D integrated “teracomputing” system-in-package (SiP) that will integrate novel materials such as carbon nanotubes in the substrate material as heat spreaders, silicon interposers with phase change materials in microfluidic channels, and integrated passives for thermal management. Optics will form the interconnects because they use less bandwidth and require less power. One thing Bottoms is pretty sure about, “all packaging and interconnect materials and most device materials will change during this decade, and will change in the next decade” to include things like nanotubes and nanowires.
Offering a market perspective on the power and importance of, Jeff Perkins of Yole Development pointed during the Tuesday morning panel discussion that “not much of a downturn has been experienced in this space because this is all about innovation.” Rather, 3D has opened up opportunities in business in terms of applications that are form factor or performance driven. He predicts that by 2015, 3D packaging will be one of many solutions available. He talked about a “3D Packaging Toolbox” which by 2013 will consist of 62% 3D TSV stacks, 18% 3D interposer modules, and 18% 3D WLP devices. He advises companies to pick their opportunities by looking for the ones that are trending toward 3D.
Perkins says the big question is still Who is the best 3D IC builder? “Has there ever been a value shift opportunity like this in the history of the semiconductor industry?” he asked. Foundries are moving fastest toward this opportunities, others are scared off by yield concerns, but there’s “still plenty to grab” he says, to get in on the action.