Last year, it was all about through silicon vias (TSVs), this year, it’s all about everything else needed to achieve 3D IC stacks using TSVs. I’m talking about 3D IC technology discussions at this year’s SEMICON West. A clear example of this was SUSS MicroTec’s workshop on wafer thinning and handling, held off site at the St. Regis Hotel on July 15.

The company lined up a formidable program, keynoted by Bart Swinnen of IMEC, and showcasing both equipment and material supplier-developed processes from Disco, 3M, Dupont, T-MAT, SUSS, Surface Technology Systems and NEXX Systems. While solutions for temporary bonding and debonding were clearly the headliner of the show, it was good to see other peripheral handling issues addressed as well.

Swinnen got things started with an overview on cost-effective 3D systems integration. IMEC has been on a mission to classify 3D integration schemes, define roadmaps, and establish supply chain ownership, because currently, the current 3D universe “is in chaos.” In summary, he explained that cost of 3D processing needs to offset against performance benefits, and also can be realized by optimizing production flow. Standardizing 3D integration schemes and roadmaps, and mapping them against the existing supply chain can help reduce 3D system cost. Finally, individual 3D product cost can be controlled by aligning technology choice with product requirements, reducing process steps and/or developing parallel processes to simplify production flow, and using known good die (KGD).

Scott Sullivan, CTO of Disco America took the microphone next, discussing processes and challenges for wafer thinning and edge trimming of carrier and device wafers. He talked about what challenges had been solved — such as grinding, breakage, and handling — and those that remain, namely thinning and exposure; post height and pitch variations; transfer of exposed post wafers; cleaning; and copper contamination. For example, one grinding solution is to mount the wafer on temporary glass carrier wafer where it can be thinned without concern for warpage, and then squaring off the edge before grinding prevents edge chipping.

Next were the feature presentations, with 3M, Dupont, and T-MAT all presenting their materials and processes for temporary bonding and debonding. Essentially competitors in the market, these companies all share the distinction of being compatible with SUSS MicroTec’s configurable bonding platform.

3M’s wafer support system process abandons traditional backgrinding tape in exchange for a spin coat liquid adhesive that laminates the wafer temporarily to a support glass carrier. UV cures the adhesive through the glass support to create a robust, solid adhesive film. The differentiating factor of the adhesive is its light-to-heat conversion (LTHC) attributes that allows for low stress removal of glass carrier from support adhesive requiring no additional heat or solvent. Rather, a laser rasters through the glass carrier to decompose the LTHC and release the glass from the adhesive. The carrier lifts off the wafer in stress free low temp method. The adhesive layer then peels off easily. Equipment requirements include a mounter, bonder, grinder, and demounter. 3M has a non-exclusive agreement with SUSS to build equipment that is configurable for this process.

Chris Milasincic, of Dupont, discussed Dupont’s temporary bonding and debonding process, which he explains avoids or mitigates thin wafer handling by using two different classifications of polyimide materials. Like the 3M process, this approach also uses laser ablation to remove the glass carrier. However, rather than a peel-away adhesive, a solvent release and adhesive removal step is used.

Franz Richter, founder of Thin Materials AG, (TMAT) explained that TMAT has focused on process development for carrier technology, developing an adhesive and proprietary layer for the debond step. He said the key element is the release layer, which can at the same time absorb shear forces to keep wafer on carrier during backgrinding, and debond easily due to the nature of the adhesive. It works with both hard and soft carrier materials, enabling handling of wafers with topography. Proprietary force-free bonding reportedly eliminates risk of wafer breakage, and the “cold” debond process means the carrier comes off clean, leaving no adhesive residue to be removed.

Wilfried Bair, SUSS MicroTec, rounded out the bonding/debonding portion of the workshop, explaining how SUSS’s latest bonding platform was developed to be configurable to all the processes presented here. He said it changes what exists, which is a toolset that works with one specific process. The intention of SUSS is to give end-users the ability to use different processes for different applications with the same tool. The key is flexibility. Device manufacturers can select a process and add capacity as needed. The company’s flagship bonder, the XBC 300 features a patented dock-and-lock system, to add capacity for higher throughput, and an intuitive software interface for ease-of-use.

The final two presentations of the day, by Art Kiegler of NEXX Systems and Michelle Bourke of Surface Technology Systems, addressed wafer handling solutions for processes that occur prior to bonding, namely etching TSVs themselves, and electroplating and PVD processes.

Kiegler noted that 3D applications are generating a variety of substrate types that require different handling solutions, for example mounted wafers, thinned only, or thinned with rim. He said that details of edge tolerances are very important, and that wafer/carrier alignment is also important to the “edge exclusion budget.” Carrier and adhesive properties affect PVD processes, and need to be considered when selecting the right handling solution. For example, electrostatic clamping is more effective for PVD because it offers some conductivity. Ultimately, Kiegler noted that standardization will be important to gain economic efficiency.

For etch processes, thin wafer handling is still a challenge, and has different issues than for bonding and debonding. Bourke explained that DRIE is an exothermic process, so getting the heat out is one of the handling concerns. Therefore, STS uses what Bourke called electrostatic clamping, (ESC) which employs a bipolar approach to ensure uniform force across whole wafer. One key advantage is the ability to clamp the carrier wafers without the need to metalize it. Bourke added that STS was also able to to successfully clamp a 700µm glass carrier with TMAT present and perform a stress relief etch process without the need to metalize the back of the carrier. ESC reportedly improves temperature control, is simpler than mechanical clamping, eliminates top surface contact on the wafer, reduces particles, lower s COO, and improves reliability.

In addition to addressing a critical technology limitation in market adoption of 3D IC integration, this workshop demonstrated how companies are changing their marketing strategy in this economic climate by finding new ways to showcase their expertise, rather than just maintaining a presence at a pivotal industry event. Photos of the event and reception afterwards can be viewed here.

If you missed the event, you can still register to recieve copies of the full presentations here on the SUSS MicroTec website.

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