Processes addressing the handling of ultra-thin wafers have been a hot topic ever since it became clear that they are vital to a multitude of semiconductor applications such as MEMS, compound semiconductors, LEDs, fan-out WLP, CMOS image sensors (CIS) and most recently, 3D IC using TSV interconnects. In fact, according to Bioh Kim, Director of Business Development for Advanced Packaging and 3D integration, EV Group, thinning is essential to continue following the semiconductor industry roadmap. Addressing a group of the Arizona Chapter of IMAPS at a regional event last week, Kim presented an update on trends in thin wafer handling and the challenges still to be faced.
According to Kim, as wafers approach thicknesses of 50µm or less, issues of mechanical stability (warpage, breakage and chipping) and handling (automation, edge contact, storage) have caused a paradigm shift from non-carrier processing to temporary bonding on a carrier. However, temporary bonding and subsequent debonding has its own set of challenges, and Kim talked about technology trends taking hold to address these.
One trend is a shift from laminate adhesives to the spin-coat variety. Kim notes this is because it offers better edge protection; is compatible with a non-flat surface particularly when you’re dealing with a patterned surface or bumped structures; remains stable at high process temperatures; and allows for a slide off debond process rather than wedge lift-off for less stress to the thin wafer. Kim added that while EVG equipment can run both laminate and spin coat processes, the company endorses the use of Brewer Science adhesives because they withstand higher temperatures when compared to lamination tapes and waxes; and have been proven stable to 300°.
Kim says there’s a trend towards using silicon carriers over traditional glass (Borofloat, Pyrex) for a number of reasons, but mainly due to thermal properties. Specifically, there is no thermal expansion mismatch between the carrier and device wafer since they’re both made of silicon, and thermal conductivity is better than glass. The cost per wafer of 300mm Si wafers is almost half that of 200mm glass wafers, and additionally 300mm glass wafers are difficult to receive, explained Kim. Both silicon and glass wafers can be reused more than 100 times, and are suited to double-sided lithography. However internal logistics are easier with silicon wafers than glass.
A third technology trend for thinning processes Kim discussed briefly was edge trimming. As wafers become thinner, conventional thinning processes put wafer edges at higher risk of chipping. Therefore, it’s become increasingly important to protect edge of wafer. Kim says that edge trimming minimizes risk of chipping.
In a joint development program with IMEC, Amkor, and Qualcomm, EVG participated in an investigation to determine the impact thinning has on chip performance. The test vehicle was a sub-micron CMOS product that was first put through an electrical test prior to thinning; and was subsequently temporarily bonded to a Si carrier wafer and thinned. It was then tested post processing, and after debonding, was subject to further physical analysis and final characterization.
According to Kim, the conclusion was that there was no change in product performance due to wafer thinning, and considering the maturity of the processes, yield loss in the subsequent packaging of thinned, stacked die is negligible.
For bonded wafers, however, questions and challenges remain. With regard to edge modification, is edge trimming mandatory? Is exposed adhesive ok for various vacuum processes? With regard to alignment, is current pre-aligner good enough? Additionally, adhesive stability is still an issue. Kim said there is a need for higher stability temperature, and improvement in the release scheme with no damages is ongoing. Performance verification with TSVs is still lacking, as is assurance that no damage is caused to bumped structures during the bonding process.
When it comes to standardization, Kim notes that while SEMI has many standards in place for dealing with 775µm thick wafers, there are none addressing bonded wafers. Citing a statement made by SEMATECH, Kim noted that “When two 775μm-thick wafers are bonded and later thinned, it creates challenges for robots, older FOUPs, wafer ports, edge trim tools, notch alignment and other portions of fabrication chain”. Thus there is a need for equipment standardization, and also standards around carrier wafers. Should they be silicon or glass; full thickness or adjusted (ground)? And what is the final standard stack thickness? While work is underway, there is still much to be done.