Test and Inspection

Cascade Microtech Breaks Through the Barriers of 3D Test
CMfig2 CMTProbeFig3

Cascade Microtech Breaks Through the Barriers of 3D Test

For quite some time, the lack of cost-effective test solutions for 2.5D interposers and 3D stacked ICs (3D SICs) has been at the top of many industry experts’ laundry list of ‘what’s-holding-up-commercialization for 3D’. First, there are technology issues: fine-pitch probing, pin count, contact force and the phenomenon of weak I/O drivers. But bigger than that, the cost of 3D test is a maj... »

3D Integration Workshop Faces Reliability Challenges Head On
yolemarkettrend copy

3D Integration Workshop Faces Reliability Challenges Head On

The Friday 3D Integration Workshop at DATE 2014 once again found me among friends, as an intimate group of about 30 gathered to spend a day sharing knowledge gained since last year’s workshop. My key take-away for the day was how to achieve reliability and robustness. Jürgen Wolf, director of the Fraunhofer IZM-ASSID 3D integration program stepped in as keynote speaker to replace Yole Développ... »

Fogale Nanotech: Building The Swiss Army Knife of 3D IC Metrology and Inspection
Fogale Nanotech World Headquarters, Nimes, France

Fogale Nanotech: Building The Swiss Army Knife of 3D IC Metrology and Inspection

In the world of 3D ICs, where features are becoming finer and submicron accuracy and precision is more important than ever to maintain intra-wafer uniformity throughout the wafer or die stacking process flow, process control by means of metrology and inspection is more important than ever. The industry offers a number of non-destructive options – optical, X-ray, scanning acoustic microscopy – ... »

Making Progress with 3D IC Design and Test

Making Progress with 3D IC Design and Test

Thank you, Ann Steffora Mutschler (Semiconductor Engineering) for getting to the bottom of the difference of EDA tools for  2.5D and 3D IC design and test, and providing such a clear explanation in your post, “Evolution vs. Revolution”. In this 2-part post, Mutschler explores the EDA vendor arguments that “tool and design flow changes need to be evolutionary, rather than revolutionary.” A... »

Progress Reports for 3D IC Thermal Management and Test
hotspot

Progress Reports for 3D IC Thermal Management and Test

In Jan Vardaman’s recent readiness report card issued at 3D ASIP in December, 3D IC thermal management issues scored and “F” for lack of a solution o the hot-spot problem when stacking memory on logic. And while she gave 3D IC test a “B” for probe card development, it got an incomplete for reliability data. At the end of her presentation, she invited anyone with new solutions to “see ... »

Page 2 of 81234»