Test and Inspection

Cascade Microtech Breaks Through the Barriers of 3D Test

For quite some time, the lack of cost-effective test solutions for 2.5D interposers and 3D stacked ICs (3D SICs) has been at the top of many industry experts’ laundry list of ‘what’s-holding-up-commercialization for 3D’. First, there are technology issues: fine-pitch probing, pin count, contact force and the phenomenon of weak...

Making Progress with 3D IC Design and Test

Thank you, Ann Steffora Mutschler (Semiconductor Engineering) for getting to the bottom of the difference of EDA tools for  2.5D and 3D IC design and test, and providing such a clear explanation in your post, “Evolution vs. Revolution”. In this 2-part post, Mutschler explores the EDA vendor arguments that “tool...

3D TSV Test Approaches: Outlook for 2014

Metrology, process control, and electrical test are key enablers for the success of the semiconductor industry. 3D integration using TSVs offers new challenges in this area that need solutions. There seems to be industry consensus that it is extremely difficult to perform a wafer-level test that ensures the complete functionality of...

Multitest: Handling the Mobility Market

What better way to wrap up a busy week at SEMICON West 2013 than a site visit? After three days of interviews and PowerPoints, I was ready for some some hands-on demonstration. Barbara Loferer, marketing manager of Multitest, was concluding an open-house week at the company’s San Jose facility to promote...