3D NAND Flash, El Capitan and Peacocks’ Tails – An Outlook for 2015
2014: That was a year that was! Many of you, perhaps remembering my outlook missive from last year, must be looking forward to how I would explain my piffle given the marvelous developments over the past year. Well, piffle it ain’t. Just more nuanced. I’ll explain but first, a recap of...
What Does Success for 3D Integration Look Like?
For the third consecutive January, I spent 3 days in Grenoble attending the European 3D TSV Summit. Each summit has followed a specific theme that aligned with where 3D integration was in its evolution. Kevin Crofton, SPTS, summed it up nicely in his closing remarks this year. In 2013, we...
Path Finding Series Part 3: The Cost of Non-robust Design
In previous posts, I discussed a process for process-centering a design. In this post, we will examine how non-robust design’s erratic yields can impact the manufacturing environment and cost of a product. A non-robust design will have at least one specification that is skewed away from the specification’s center as...
What’s Different for 3D Stacked DRAM Equipment Shipments in 2015?
Why DID you miss your 2014 3D Stacked DRAM equipment shipment forecast? And what’s different about the outlook for 3D Stacked DRAM equipment shipments in 2015? Briefly, as presented in Part 1 of this thread, significant structural problems existed in the DRAM industry, present from the very beginning of 2012, that...
Finding the Right Time and Place for 3D ICs
As a cost modeling company, when we were asked to speak at 3D ASIP this past December, the initial topic choice seemed fairly obvious. We decided to tackle the question of whether the cost of 3D ICs will ever be low enough for HVM. We’ve done a lot of individual...
What does 3D integration have in store for semiconductor and related industries in 2015?
Yole Développement invites you to discover the main technology trends and business opportunities for 3D integration in 2015. As a research market & strategy consulting company, Yole Développement (Yole) works with the leaders of the advanced packaging industry every day to understand technical challenges and market issues. In this article,...
Understanding Heterogeneous 3D Integration
“How is heterogeneous 3D integration defined?” There are certainly different understandings in the microelectronics community regarding the definition of heterogenous 3D integration. In a very general definition, it is defined as the 3D integration of different devices such as a CMOS processor and a memory, for example. A more limiting specification would...
Defining Test Access Between Stacked Die
Accelerating the adoption of interposer and 3D designs depends on several advances across the design and manufacturing ecosystem. Standards are a part of the ecosystem. Now, stay with me. I know standards put some people to sleep, but I won’t be going into any gory details, just talking about the...
Why is it Taking so Long to Ramp Interposer and 3D IC Designs?
And what are we going to do about it in 2015…? A moment ago I finished reading my predictions for 2014. I wrote them on January 11, 2014, almost exactly one year ago. After convincing myself that I was roughly on target, I am going to stick my neck out again,...
Executive Interview: Si2 Aims to Boost Confidence in Designing 3D ICs
There’s no doubt left in the minds of semiconductor device manufacturers that the processes required to build interposer-based and 3D IC devices are matured and ready for production. However, the jury is still out in the design community because designing 3D ICs still poses a challenge. Si2 has set out to...
Why You Missed Your 2014 3D Stacked DRAM Equipment Shipment Forecast
Remember SEMICON West 2012? How could you forget? It was all clubbing with your customers at The Redwood Room, DNA Lounge, and The Endup after a few standout meals with them at Mission Chinese Food, Slanted Door, Wayfare Tavern, Acquerello, and Absinthe that were preceded by a few drinks with...
The Cost of 3D ICs
When 3D integration has been discussed in the past, whether in terms of a true 3D IC stack or an interposer-based design, the cost of 3D ICs has not always been part of the discussion. In the past couple of years, as 3D ICs have moved closer to reality, more attention...
Popping the Cork on 3D IC at IEEE 3DIC 2014
The IEEE International Conference on 3D System Integration (3DIC) was held in Kinsale, Cork, Ireland in December, 2014. The three day conference covered all 3D IC topics, including 3D process technology, materials, equipment, circuits technology, design methodology, thermal effects and applications. The 2014 conference was very successful with a great...
2015 Industry Outlook: SPTS Predicts its 3D Etch, PVD and CVD will reach HVM
In June 2014, SPTS co-produced a webinar with Ron Huemoeller of Amkor, titled “2.5D and 3D Packaging at the Tipping Point.” We forecasted that significant product announcements would be made over the next 18 months and we were right; sk Hynix, Samsung and Micron all announced readiness for their 3D stacked memory...
IEDM 2014 3D Short Course Highlights 3D Memory Cubes for SYSTEM design
Years ago, when I gave my first 3D technology presentations, I noticed very different reactions from my diverse audience: The packaging engineers were in their element, engaged right away and asked detailed technical questions. The IC designers appeared quite worried about the strange — and for them, at that time...
2015 Industry Outlook: EDA Reaches an Inflection Point
As our industry moves towards the commercialization of 2.5 and 3D Integration, also known as complex packaging integration (CPI), we see some critical inflection points materializing in the EDA marketplace. Existing tools have worked well for us up to this point, but now the design considerations have changed dramatically. If...
Path Finding Series Part 2: What if I do not have a robust design?
In previous posts, I discussed Robust Design analysis as orthogonal Path Finding. This analysis is performed while the design implementation is held constant but with varying manufacturing process parameters. This will determine how sensitive a design is within the process(es) it will be manufactured. The previous post highlighted the negative...
3D ASIP 2014: All Aboard the 3D IC Train!
Like the previous 10 years, RTI International held the 11th 3D-IC focused conference in early December. Instead of the usual two and a half days, this year it spanned 3 days, because it also offered a 4-hour session about 3D design challenges and solutions available from foundries, EDA and IP...
3D ASIP 2014 Sparks Mixed Reactions from the Media
Isn’t it interesting how different people attending the same event can come away with different perspectives? I attended last week’s 3D Architectures for Semiconductor Integration and Packaging (3D ASIP 2014), and came away feeling euphoric about what the 3D industry has achieved since last 3D ASIP, and all its promise...
Happy Holidays from the 3D InCites Family to Yours!
