DARPA Chooses 11 teams to kick off NGMM
DARPA has selected 11 organizations to begin work on the Next-Generation Microelectronics Manufacturing (NGMM) program. The Phase 0 effort will establish foundational research to inform the next steps toward creating a domestic center for fabricating 3D heterogeneously integrated (3DHI) microsystems.
Selected teams are:
- Applied Materials
- Arizona State University
- Intel Federal
- NC State University
- Raytheon Technologies
- Northrop Grumman Space Systems
- Northrop Grumman Mission Systems
“We’re confident these teams will help build a sustained path toward an R&D ecosystem that provides the framework for future 3DHI innovation,” noted Dr. Carl McCants, special assistant to the DARPA director for the Electronics Resurgence Initiative (ERI).
NGMM’s Phase 0 teams are working to define, analyze, and make expert recommendations for 3DHI microsystems. In addition, they are identifying the equipment, processes, hardware, software tools, and facility requirements to manufacture these microsystems. The results of these detailed analyses will inform future program phases and efforts.
NGMM is a key to ERI 2.0, a DARPA initiative to ensure domestic leadership in cross-functional, future-focused microelectronics research, development, and manufacturing. Built on collaboration with industry and academia, ERI 2.0 targets national-level microelectronics concerns through a thematic portfolio of programs aimed at U.S. national security and economic interests.
DARPA’s 2023 ERI Summit in Seattle, Aug. 22-24, will offer a forum for further discussion.
TSMC Delays US Fab Opening
Recently, the company announced that it was sending more Taiwanese workers to the U.S. to manage the final stages of making the plant operational. Now according to Nikkei Asia, that move has proven insufficient.
“We are encountering certain challenges, as there is an insufficient number of skilled workers with the specialized expertise required for equipment installation in a semiconductor-grade facility thus we expect the production schedule of N4 [4-nanometer] process technology to be pushed out to 2025, ” said TSMC chair Mark Liu.
Japan’s Rapidus Developing Next-Gen IC Technologies
Digitimes Asia reports that as Japan is developing the technology for mass-producing 2nm chips, they are not only trying to increase the transistor density on a single die but also to combine multiple dies with heterogeneous integration.
Japan reportedly wants to get back into the leading-edge semiconductor business and in Dec 2022 formed a new company, Rapidus, to reboot its semiconductor industry. Rapidus has the backing by leading Japanese technology and financial firms, including Denso, Kioxia, Mitsubishi UFJ Bank, NEC, NTT, Softbank, Sony, and Toyota Motor. The Japanese government is also subsidizing Rapidus.
The company announced a partnership with IBM to develop 2nm technology in fabs that Rapidus plans to build in Japan during the second part of this decade. The IBM process uses gate-all-around transistors. While business details were not disclosed, Forbes speculates that there are likely two parts to the deal: a cross-licensing agreement for the intellectual property necessary to build the product and a joint development agreement. While the announcement is nominally for IBM’s 2nm process, it likely includes a long-term commitment to build advanced semiconductor chips going beyond the 2nm process node.
Rapidus has also announced a collaboration with IMEC on advanced semiconductor technologies. The company has focused on heterogeneous integration (HI) since its establishment in August 2022, trying to combine multiple dies in a single system using 2.5D and 3D integration. The Japanese Ministry of Economy, Trade, and Industry (METI) revamped has identified 2.5D and 3D packaging and silicon bridge technology as the technologies necessary to make a breakthrough by the late 2020s. METI aims to launch the Leading-edge Semiconductor Technology Center (LSTC) to lead the efforts, collaborating with Rapidus and overseas research institutions and manufacturers to jointly develop these technologies and to apply the advanced packaging technology to sub-2nm chips in the latter half of the 2020s.
Jay Lewis to Lead CHIPS NSTC
Jay Lewis has joined the CHIPS for America Research and Development Office (CHIPS R&D) to provide executive leadership of the programmatic and functional areas within CHIPS R&D that support the National Semiconductor Technology Center (NSTC).
Lewis joins CHIPS for America from Microsoft, where he developed a partnership with the U.S. Department of Defense to secure a domestic supply of leading-edge semiconductors and ran initiatives to promote microelectronics innovation, including for national security. Prior to joining Microsoft, Lewis was the deputy director of the Microsystems Technology Office at the Defense Advanced Research Projects Agency (DARPA), a research and development arm of the U.S. Department of Defense. At DARPA, Lewis oversaw a large portfolio of microelectronics programs and helped to transition several innovations to commercialization.
The NSTC aims to support and extend U.S. leadership in semiconductor research, design, engineering, advanced manufacturing, and the semiconductor workforce. The goals of the NSTC are to advance critical semiconductor research and development; expand access to design and manufacturing resources and allow industry, academia, and government to build on each other’s work; and reduce the time and cost of bringing technologies to market.
The NSTC will be operated by an independent, nonprofit entity. Lewis will lead CHIPS R&D’s relationship with the anticipated nonprofit entity, as well as represent the CHIPS R&D-sponsored NSTC programs before leaders in government and industry, advisory committees, and at national and international conferences and forums.
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