I was happy to share the 3D stage as a contributing editor in this week’s issue of AP Semi-monthly. In fact, I found Yann Gillou’s guide to 3D vernacular: 3D Lingo-Getting it Straight really helpful for sorting out the differences between 3D configurations at the package and IC levels, and TSV. Gillou and I met last October at SEMICON Europa, where he explained to me how TSV is often identified as a 3D configuration by itself, when it reality, it is what he calls a “techno brick” used to achieve “real” 3D ICs. It was great to read the final article inspired by this conversation. It’s definitely worth the read.

I was also glad to see 3D ASSM’s presentation at Pan Pacific Symoposium in Hawaii get some ink from George Riley in The Riley Report. Only a month and a half away from the official kick-off, over 45 organizations from the industry, academia, and government have rfeportedly put forth efforts through the planning stages. Riley’s column offers a comprehensive look at the challenges to be overcome if the development of this system-on-wafer technology is to succeed. Just in case you missed these articles in the original eNewsletter, I’ve taken the liberty of linking to them from here. – F.v.T.

Francoise von Trapp

They call me the “Queen of 3D” because I have been following the course of…

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