Heterogeneous Integration enabled by Advanced Packaging Leads the Way at SEMICON West 2016
I have to admit, after attending this week’s SEMICON West 2016, I’m feeling a little smug. Why? Because after years of waiting in the shadows for its day in the sun, advanced packaging is finally getting its turn, thanks to the push towards heterogeneous integration, which relies on advanced packaging technologies to integrate a multitude of disparate technologies including MEMS and sensors, logic, memory, RF and what have you.
I have believed in the importance of emerging advanced packaging technologies since I first joined the editorial team of the now defunct Advanced Packaging Magazine; so much so that I staked my career on it by dedicating 3D InCites to the pursuit of 3D integration and its enabling processes and platforms (through silicon vias, (TSVs), die and wafer stacking, monolithic 3D, system-in-package (SiP), package-on-package (PoP), advanced wafer-level packages (WLP), and interposer integration) all in the pursuit of heterogeneous integration. So for advanced packaging to be acknowledged as the path to next-generation devices at SEMICON West, where traditional CMOS scaling has always had top billing, is, quite frankly, HUGE. So yeah, I’m feeling a bit self-righteous right now.
What brought this on was repeatedly hearing from industry leaders throughout the week that while efforts in traditional scaling will continue, it’s no longer the driver for achieving next-generation performance, power and speed requirements for our computing devices, from high-end, high-performance computing to those that will power the Internet of Things (IoT).
At imec’s ITF-USA that took place Monday, July 11, 2016, before SEMICON West was in full swing, CEO Luc van den hove said that disruption has turned our industry upside down. “As users, we are enjoying services that were not possible 20 years ago, thanks to companies that dared to take a different view,” he said, pointing to sharing-economy companies like Uber, Facebook, and Air BnB that rely on app-based technology to exist. While van den hov says scaling “must continue to enable the IoT wave to generate compute power and storage capacity” it will require more than just geometry-based scaling, and will be based on system-level, heterogeneous integration into the third dimension.
Even Gordon Moore himself (via a video interview with van den hove earlier this year), said he wouldn’t be surprised if scaling comes to an end in the next ten years, and that he’s been repeatedly surprised that engineers have come up with new ways to overcome seemingly insurmountable barriers. “Predicting major innovation is a tough job, and I will leave it to someone else,” noted Moore.
More evidence to the rise of advanced packaging technologies can be seen in the demise of the International Roadmap for Semiconductors (ITRS), which Bill Bottoms reported has published its final version. (Not next version; but actually the LAST ITRS roadmap ever). It’s been replaced by the Heterogeneous Integration Roadmap, “Progress is not going to paced by scaling transistor size, because as we get smaller we’re not getting gain we expected,” explained Bottoms in his talk during the Advanced Packaging Forum’s SiP session. “We are moving from scaling to heterogeneous integration.” The key enablers will be in scaling the interconnect and using the third dimension to achieve power cost, lower power, higher performance with improved reliability and latency. “All of these innovations we are hearing about are a down payment on the revolution that has to take place,” he said, adding that 3D silicon and heterogeneous integration road mapping is designed to identify roadblocks with sufficient lead time and enable pre-competitive collaboration, reducing cost and time to bring innovation to market and maintain industry growth.
Need more proof that the advanced and 3D packaging stars are on the rise? During the Advanced Packaging Forum, TSMC’s Doug Yu announced the company’s new goal is to grow from the world’s leading IC foundry to the industry’s first SiP foundry. “We are a wafer foundry, but we are doing some packaging business to survive and grow,” noted Yu. “Moore’s law is becoming more challenging, so we are preparing for those days.” TSMC focuses on wafer level system integration (WLSI). He said they realized if they wanted to do high-performance, high-end packaging, it needed to be done in wafer form to leverage TSMC’s core competence, infrastructure, and expertise. “Achieving micron scale is easy when you’re used to doing nanometer scale processing,” he said. The company has achieved two industry firsts already; it was the first to deliver Si interposer chip-on-wafer-on-substrate (CoWos) for high-performance computing; and the first to propose and realize integrated fan-out (InFO) PoP for mobile SiP applications. The goal to now become the first system integration foundry represents a new paradigm in the industry.
Other speakers at the forum validated Yu’s sentiments. ASE’s, CP Hung noted that TSVs enables maximum performance and minimizes SiP footprint. WL SiP with TSVs is the next wave of packaging miniaturization. nVidia’s John Hu described the ultimate 3D System (Fig 1), noting the merging of the chip interconnect and package in a 2.5D/3D SiP world.
Admittedly, SEMICON West 2016, with its theme of “definitely NOT business as usual” was about a much, much more than a shift in focus towards advanced packaging, and I’ll get into all of that, and what’s driving that in subsequent blog posts next week. But for me, one of the most significant changes underway is the realization the heterogeneous integration enabled by advanced packaging technologies is slowly but surely replacing Moore’s law to realize the next-generation of computing. ~ F.v.T.