As Dick James, Chipworks, puts it, the SEMI Advanced Manufacturing Conference is “… an annual conference focused on the manufacturing of semiconductor devices; in this it differs from other conferences, since the emphasis is on what goes on in the wafer fab, not the R&D labs, and the papers are not research papers – some are better described as ‘tales from the fab’! After all, it’s the nitty-gritty of manufacturing in the fab that gets the chips out of the door, and this meeting discusses the work that pushes the yield and volumes up and keeps them there.” (See more from Dick about SEMI ASMC, including some trip-down-memory-lane TEMs, in this excellent piece.)

In my previous SEMI ASMC 2016 post, I highlighted a sampling from the rich variety of topics covered at the conference; here, I want to drill down into the specifics from ASMC 2016 Session 15, 3D/TSV, whose co-chairs were Professor James Lu, RPI; Thuy Tran-Quinn, IBM; and Russell Dover, Lam Research. (By the way, the combination represented in the co-chairing duties here, Academia-IDM-Supplier, perfectly captures the rich mix that makes ASMC unique.)

Rusty in the ClubOnce is chance, twice is coincidence, third time is a pattern. The fifth time, which is how many years running 3D/TSV sessions have been on the SEMI ASMC agenda, cements and makes it official: 3D/TSVs have made the advanced manufacturing club!

At least that’s my take on the subject.

Paper 15.1, “Process Development and Optimization for High-Aspect-Ratio Through-Silicon Via (TSV) Etch,”  presented by Kumarapuram Gopalakrishnan, provided us with an overview of TSV integration at GLOBALFOUNDRIES, a description of GF’s TSV process flow (via-middle flavor), and a deeper dive into the TSV etch itself.

Being an old plasma etch hand I particularly appreciated the extensive characterization work GLOBALFOUNDRIES performed evaluating the tradeoffs between classic Bosch process etching of deep silicon vias and the “Steady State” etch process that is its rival.

(You will remember how the Bosch process alternates between high rate, relatively isotropic etching steps, and deposition process steps, during which a polymer is laid down to protect the deepening sidewalls from further isotropic etch attack. “Scallops” are the result, sidewall roughness that must somehow be managed by either shortening the process step times and / or increasing the rate at which the process steps switch.  Either that or the scallops are dealt with post-etch.)

The GF authors concentrated on undercut and notch control, ran an extensive DOE to improve TSV etch depth uniformity, worked on via dimensional scaling, optimized silicon etch rates for high-volume manufacturing (HVM) cycle time improvements, and characterized and solved the riddle of an etch defect called a silicon fin defect, which they traced back to the presence of bulk micro defects (BDM) in the starting silicon.

The end result? Nothing less than an industry-leading TSV etch process with a CpK > 1.67.

Now that’s advanced manufacturing.

Moores WallPaper 15.2 was on “Non-Conductive Film Underfill for 3D Integration of 30 μm-Thick LSI Wafers with Fine Cu-TSVs,” and was the work of an old ASMC friend, Mariappan Murugesan, and his co-authors from The Global INTegration Initiative (GINTI), Japan / Tohoku University.

Asking the question “Why does the world need thin wafers?” leads to the answer that thinner wafers / thinner die allow for smaller TSV diameters which allow for less TSV capacitance and a greater number of TSVs per unit area, and that more of those better interconnects opens the door to better system performance.

But the residual stress in thin wafers, along with the different mechanical characteristics of thin silicon, can have deleterious effects on device performance and reliability.

Non-conductive film underfill to the rescue. GINTI’s studies show that NCFUF plays a vital role in minimizing residual mechanical stress in die/wafers as thin as 20µm.

Silicon as a Mechanical Material” is the ur-paper on MEMS written by the legendary MEMS guru Kurt Petersen in 1982 and, as the work by GINTI shows, it is just as important today to consider and manage the mechanical properties of silicon in our thin-die 3D/TSV world.

The final paper in Session 15 was an excellent student paper, 15.3, “Advanced Detection Method for Polymer Residues on Semiconductor Substrates,” by Helene Richter and her co-authors from Fraunhofer Institute for Integrated Systems and Device Technology, and ams AG. SEMI ASMC has a long history of encouraging and recognizing the contributions of students in the field, and the Richter paper was a terrific example of just why that’s so.

PittAs explained above, the Bosch process for etching deep silicon structures relies on the deliberate deposition of an etch-blocking polymer, the formation, and removal of which necessitates close management. Excessive polymer creation leads to etch defects, which in turn can lead to defects in post-TSV etch metallization.

Yield killers.

By impregnating Bosch process polymer with fluorophores, and then by examining the now-fluorescent polymer material under a confocal laser scanning fluorescence microscope, the polymer can be clearly imaged optically and nondestructively; an essential part of managing it.

It may be a costly myth to say “If you can’t measure it, you can’t manage it,” (pace W. Edwards Deming), but Helene Richter and team sure made a great case for the success with which polymer-created etch defects can be imaged and quantified using the accurate film representations illuminated using their technique.

SEMI ASMC is an unparalleled venue for semiconductor professionals to share tradecraft and learn the latest information in the practical application of advanced manufacturing strategies and methodologies, and in its 27th installment proved itself of value once again.

Those advanced semiconductor manufacturing strategies and methodologies are just as important now in 3DIC/TSV as they have been to any of the many other process flows discussed at the conference, starting from ASMC Year 1.

3D/TSV, welcome to the advanced manufacturing club.

From Santa Clara, CA, thanks for reading. ~PFW

Paul Werbaneth

Paul Werbaneth is a long-time Contributing Editor at 3D InCites. Since entering the semiconductor industry…

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