Advanced Packaging and 3D come to MRS Spring Meeting
For the first time ever, the Materials Research Society (MRS) brought its annual Spring meeting to Phoenix. I have never attended this event, as it is deeply academic, and has not been on my radar for 3D or advanced packaging technologies. However, after finding out from fellow SemiSisters, Rozalia Beica, Yole Developpement, and Nancy Stoffel, GE Global Reseach, that there was an advanced packaging session for the first time ever: Materials Frontiers in Semiconductor Advanced Packaging, chaired by Stoffel and Jian Wei Dong, Dow Electronic Materials. There was also a paper on micro and nano computer tomography X-ray for 3D IC stacks delivered by Fraunhofer IPFTs’s Ehrenfried Zchech, I decided to pop in for the afternoon.
I ran into fellow technology journalist, Katherine Derbyshire, in the Advanced Packaging session. As an expert in thin-film manufacturing, Derbyshire has historically focused her coverage on front-end semiconductor technologies, so I was intrigued to find her in my queendom. She said it’s because advanced packaging is finally becoming a value-add to semiconductor manufacturing. I’ve noticed a lot more attention being paid to that topic on Semiconductor Engineering. I have to admit, I was feeling rather smug when she said that. As my entire semiconductor career has focused on advanced packaging and 3D integration, I’ve always been a believer. In any case, since I don’t have the scientific pedigree that Derbyshire has, I am really looking reading and sharing her post/s from this event.
Beica set the stage for the packaging session with a high-level presentation on the Future of Advanced Packaging. As this presentation was targeted to a new audience, she delivered a comprehensive view of the market evolution, packaging trends, computing trends, market drivers, and various package platforms with complete with product teardowns. One of the key takeaways from the materials perspective is that they need to serve a wide process window, as there is a broad range of packaging technologies from low, to mid and high range. Other key points included:
- Flip-chip is still the dominant platform and will continue to grow, however, it could be significantly impacted by lower cost alternative platforms such as fan-out wafer level packages (FOWLP).
- If Apple adopts TSMC InFO for its A10 APU processor in the iPhone 7 as predicted, then FOWLP could be a $2B business by 2020.
- Fan-in is a mature technology, however, due to low cost and form factor, it is still a platform of interest in the industry.
- 2.5D and 3DIC is already in production with CMOS image sensors, FPGAs, and MEMS. Most recently is the gaming processor unit (GPU) and high bandwidth memory (HBM) integration on an interposer.
I did not catch the remaining presentations in the session — which featured Georgia Tech’s developments in glass-based device and systems packaging as an alternative to CMOS scaling; one on sustainable material, from Purdue University; and presentations from TSMC and Hitachi Chemical on material challenges and technologies for wafer-based and stacking approaches —, because I wanted to catch Zchech’s presentation, scheduled simultaneously.
Zchech explained that when through-silicon vias (TSVs) are used as the method of interconnect in die stacking, the quality of the contacts (TSVs and solder bumps) is critical to performance. X-ray computer tomography (XCT) is a good characterization technique for obtaining information about these structures in a non-destructive way. However, current micro XCT are limited to detecting 1µm and above. Characterization in nanometer range below 100nm is performed using scanning electron microscopy (SEM) and transmission electron microscopy (TEM), both which require cross sections and are destructive methods. There is a gap between this neo-analysis and non-destructive testing that lies in the sub-micron space that Zchech says can be filled using sub-micron XCT. Not only that, but his team has built its own tool to do it. He graciously contributed his abstract and presentation for publication on the 3D InCites Knowledge portal. You can read it here. ~ FvT