Latest Posts
3D-TEST Workshop Does What Its Name Says: Concentrates On 3D-Test
Virtually all scientific and industry forums on 3D have “3D design-for-test” and/or “3D test” on the topic list of their...
Designing in 3D? Don’t Make These DFT Mistakes
The semiconductor industry hasn’t adopted 3D ICs as quickly as many in the industry expected. There are some barriers that...
Making Progress with 3D IC Design and Test
Thank you, Ann Steffora Mutschler (Semiconductor Engineering) for getting to the bottom of the difference of EDA tools for 2.5D...
Cadence Design Systems: Encounter Test
Product Description Cadence Encounter Test provides a comprehensive methodology for 3D-IC design-for-test and automatic test pattern generation that includes a...
2013 3D Test Workshop Call for Papers
The 2013 3D-TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional stacked ICs (3D-SICs), including Systems-in-Package (SiP), Package-on-Package...
3D ICs News in Brief – Jan. 19-29
While there is still a lot to report about the European TSV Summit, I wanted to catch everyone up on...Cost of 3D Test: Could it be a Showstopper for TSVs?
You all know I hate to be the bearer of bad news, but I’ve been talking to Al Crouch, Chief...
