You all know I hate to be the bearer of bad news, but I’ve been talking to Al Crouch, Chief Technologist, Core Instruments at ASSET InterTech, and he has some grave concerns that ultimately the cost of test, if not handled properly, could kill 3D TSV integration. On the bright side, it’s not too late, if awareness is raised and the proper steps are taken with developing test methodologies. I caught up with Al at the 12th Annual BITS Workshop, in Mesa AZ, where he presented the opening speech during the welcome dinner. He’s been very involved in IEEE P1838 3D Test Working Group, which recently determined that a 3D standard is needed to cover 3D chips.
Al made some really great points in his presentation, offering some analogies that explained them well, at least to me, and I thought it would be worthwhile sharing them with you. We’ve talked before about built-in self test (BIST) and how 3D will require much more “embedded content” to allow test, debug, and characterizations. If you think about a stack of die as a bank of elevators in a skyscraper, where some are express and some stop at specific floors, affecting the time it takes to travel from the first floor to your destination floor, the same is true with testing chips on different stacks through TSV “wires”. The longer it takes to test the stack can greatly affect the cost of test, where time is money.
Another important point to consider is that up until now, the PCB world was unaffected by Moore’s Law. Board pin-out didn’t change along with the functionality of the package being mounted on it. But with 3D, Moore’s Law comes into play at the board level, because there are whole systems of logic on each of those stackable die and each of those die have tons of test and debug requirements.
Crouch believes one of the four approaches being considered by the work group, The 1149.7 to Prime TAP (Test Access Point) on Each Die Proposal, would be the most cost-effective solution that addresses these concerns. In this approach, there is one 1149.1 TAP on each die that becomes the controller for all JTAG-Compatible functions. It locally provides control signals for all JTAG-compliant objects in each die.Then,two TSVs on each die deliver the signals to the single Prime TAP on each die. It’s similar to testing a multi-chip module because each die is a complete system.
Crouch explained that we’re ultimately testing silicon on a PCB test budget. The semiconductor industry is used to spending upwards of $1M on a tester, where the board testers spend 10s of thousands. Once again though, it’s all about collaboration and proceeding with caution, considering costs to all participants in the supply chain. Wouldn’t it be tragic if the 3D integration became a reality in the foundries and OSATS, only to gather dust on the shelves as IDMS and contract manufacturers opt for more affordable solutions? Luckily, designing for test from the outset using a realistic methodology could prevent that from happening.