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We have another great conference coming up for the 3D InCites community! Taking place in Dallas, Texas from May 27-30, this year’s Electronic Components and Technology Conference (ECTC) is packed with member sessions and exhibits. We have 16 members presenting, 27 exhibiting, and even more attending. This conference is the...
Advanced wafer-level packaging advances the next wave of innovation in global chip manufacturing TEMPE, Ariz. – March 19, 2024 – Arizona State University (ASU) and Deca Technologies (Deca), a premier provider of advanced wafer- and panel-level packaging technology, today announced a groundbreaking collaboration to create North America’s first fan-out wafer-level...
What an energizing week I had at IMAPS DPC 2023! I’ve said it before, but it’s worth saying again, the IMAPS Device Packaging Conference (IMAPS DPC) is one of my favorite annual events, and this year’s edition did not disappoint. There was a record turnout, great keynote talks, panel discussions,...
I have a confession to make. Last March – we’re talking March of 2023 at IMAPS DPC – Beth Keser, IMAPS president, presented me with a signed copy of the book she co-edited with Steffen Khröhnert – Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces:...
IFTLE (Insights From the Leading Edge), believe it or not, has reached #500! I hope this message reaches all of you free of COVID and ready to move on in this exciting period for Advanced Microelectronic Packaging. For those of you that have not been on board for the full...
Of all the companies that have supported 3DInCites over the past 10 years, none has been more consistently involved, both as contributor and sponsor, as EV Group. In fact, without EVG’s belief in our mission and their sponsorship the first three years, I doubt 3DInCites would still exist today. Therefore,...
Over the years, the semiconductor industry has relentlessly focused on shrinking gate dimensions to drive performance. This focus has now transitioned to the packaging side as customers are shifting from wire bonding to flip chip for use in wafer level packaging (WLP). According to VLSI Research, about 35% of chips...
There is an active and robust supply chain currently supporting these wafer sizes in the semiconductor manufacturing industry: 3”; 4”; 6”; 200mm; 300mm; and 330mm. This wide range of substrates is successfully being used today for “sweet-spot’ manufacturing of LED, compound semiconductor, MEMS, trailing-edge CMOS, leading-edge CMOS, and fan-out wafer...
For quite some time on 3D InCites, we’ve talked about how breaking up SoC designs into specific functions not only offers a lower cost of ownership than continued scaling, but also allows for heterogeneous integration of disparate technologies that are manufactured at their optimal nodes and then stacked on an...
No SEMICON West would be complete without a few laps around Moscone North and South, and some one-on-one chats with suppliers. I stopped in to see several semiconductor supplier companies who annually request an audience with the Queen of 3D to talk about their latest accomplishments, as well as gain...
