Search Results

Matches for your search: "fan-out wafer level packaging "

ECTC 2025

ECTC 2025 Member Preview

We have another great conference coming up for the 3D InCites community! Taking place in Dallas, Texas from May 27-30, this year’s Electronic Components and Technology Conference (ECTC) is packed with member sessions and exhibits. We have 16 members presenting, 27 exhibiting, and even more attending. This conference is the...

Fan-out wafer-level packaging research

Arizona State University and Deca Technologies to Pioneer North America’s First R&D Center for Advanced Fan-Out Wafer-Level Packaging

Advanced wafer-level packaging advances the next wave of innovation in global chip manufacturing TEMPE, Ariz. – March 19, 2024 – Arizona State University (ASU) and Deca Technologies (Deca), a premier provider of advanced wafer- and panel-level packaging technology, today announced a groundbreaking collaboration to create North America’s first fan-out wafer-level...

IFTLE 500: We’ve Come a Long Way, Baby!

IFTLE (Insights From the Leading Edge), believe it or not, has reached #500! I hope this message reaches all of you free of COVID and ready to move on in this exciting period for Advanced Microelectronic Packaging. For those of you that have not been on board for the full...

10 Years of Invent, Innovate, Implement at EV Group

Of all the companies that have supported 3DInCites over the past 10 years, none has been more consistently involved, both as contributor and sponsor, as EV Group. In fact, without EVG’s belief in our mission and their sponsorship the first three years, I doubt 3DInCites would still exist today. Therefore,...

Advanced Packaging Trends, Part I: Solving PR Strip and UBM/RDL Challenges

Over the years, the semiconductor industry has relentlessly focused on shrinking gate dimensions to drive performance. This focus has now transitioned to the packaging side as customers are shifting from wire bonding to flip chip for use in wafer level packaging (WLP). According to VLSI Research, about 35% of chips...

Panel Level Packaging: One Size Fits All?

There is an active and robust supply chain currently supporting these wafer sizes in the semiconductor manufacturing industry: 3”; 4”; 6”; 200mm; 300mm; and 330mm. This wide range of substrates is successfully being used today for “sweet-spot’ manufacturing of LED, compound semiconductor, MEMS, trailing-edge CMOS, leading-edge CMOS, and fan-out wafer...

Semiconductor Supplier Updates from SEMICON West 2015

No SEMICON West would be complete without a few laps around Moscone North and South, and some one-on-one chats with suppliers. I stopped in to see several semiconductor supplier companies who annually request an audience with the Queen of 3D to talk about their latest accomplishments, as well as gain...