2018 TSMC Technology Symposium: Listen – Analyze – Act

2018 TSMC Technology Symposium: Listen – Analyze – Act

May 1st is a holiday in many countries, but not in the U.S. and not for TSMC. A very professional TSMC team and many of its Open Innovation partners demonstrated recent accomplishments to a gathering of more than 2000 attendees at the 2018 TSMC Technology Symposium at the Santa Clara Convention Center. TSMC’s strategy to listen to market needs, analyze how best to meet the requirements and act accordingly demonstrated again how well this approach works. Here are highlights I captured out of the vast amount of business and technical information the TSMC speakers presented:

In his introduction, David Keller, President of TSMC N.A., highlighted that the pace of innovation is accelerating, and more collaboration is needed to profit in a market with product life cycles getting as short as only six months. He stated that in 2017, North America was again TSMC’s largest market (71% of revenue, with over 5000 individual designs). Keller also outlined how TSMC applies technology leadership, design enablement and manufacturing excellence to serve their main markets: mobile, high-performance computing (HPC), automotive and internet of things (IoT) applications.

Dr. C.C. Wei, TSMC President, and Co-CEO conveyed that artificial intelligence (AI) and 5G are the key drivers of our industry’s growth and reminded the audience that TSMC is committed to being a trusted technology and capacity partner. To demonstrate this commitment, Wei mentioned that TSMC employs more than 6000 research and development (R&D) experts and was first with 28, 16 and 10 nm as well as chip-on-wafer-on-substrate (CoWoS) and integrated fan-out (InFO) production. Regarding capacity: TSMC shipped 11 Million 12“-equivalent wafers and will increase CapEx by $1B to $12B in 2018.

Dr. Y.J. Mii, Sr. VP Technology R&D, focused his talk on the speed, area/cost, and power benefits N7, N7+ and N5 bring to customers. For example, N7 is 35% faster or 65% lower power, compared to N16 FF+. Also, N5 will be 15% faster, versus N7. Mii also stated that TSMC uses extreme ultraviolet (EUV) lithography in production today and will deploy multi-layer EUV for N7+ and N5.

Mii also outlined several ongoing development projects: Replacing the fin in FinFETs with several vertically stacked nanowires, enabling an all-around gate. MRAM, RRAM, and PCRAM development projects will be completed. Ultra-low power processes, e.g. N12 ultra-low power (ULP) and ultra-low leakage (ULL) are in progress to serve IoT and mobile applications. With bipolar CMOS-DMOS (BCD), gallium nitride (GaN) and silicon carbide (SiC) technologies, TSMC will serve high voltage applications. Last, but certainly not least for 3D InCites readers, Mii hinted that larger interposer will become available in early 2019 and other advances in IC packaging technologies will be detailed by Doug Yu in the afternoon.

Dr. Cliff Hou, VP Design and Technology Platform, focused on the availability of intellectual property (IP), electronic design automation (EDA) tools and design methodologies. Hou showed many slides detailing IP availability of IP and qualification status of design tools from Ansys, Cadence, Mentor, and Synopsys. Hou explained why N7+ is 20% denser and 10% lower power than N7 and announced a porting methodology to N7+. For N5, release 0.5, will be available in June 2018. For new packages, he only disclosed that design enablement is available, but left further details for Doug Yu to explain.

J.K. Wang, VP Operations, focused on capacity and quality topics. While TSMC plans a 9% total capacity increase during 2018, N10 and N7 capacity will double in 2018 and triple it in 2019, versus 2017. Wang also stated that TSMC offers silicon-on-insulator (SOI) support and readies a number of other technologies to meet high-voltage and low-power requirements. When talking about his team’s efforts towards ZERO defects and quality excellence in general, Wang proudly explained that TSMC realizes that automotive applications, in particular, require outstanding quality and reliability. His fabs monitor the quality of incoming materials. Also, every fab deploys many sensors and applies Machine Learning and big data analysis to quickly find the root cause of an excursion and correct it.  Predictive maintenance is applied to every tool, to preempt excursions.

Dr. BJ Woo, VP Business Development, started the series of afternoon presentations. Data traffic from 2010 to 2020 is growing at 50% CAGR. 5G and AI will be key technologies to sustain this ramp. Woo also explained which processes are best suited for specific applications and showed why N7 will be, like 28 and 16nm, a “long node” and deployed for automotive applications.  Woo also confirmed TSMC’s commitment to SOI, stated that TSMC has already shipped more than 100,000 SOI wafers and projected that RF SOI will be an essential technology to win 5G designs.

Dr. Doug Yu, VP Integrated Interconnect, and Packaging outlined TSMC’s commitment to enhancing and expanding their advanced IC packaging capabilities. In addition to new CoWoS and InFO / InFO_PoP platforms, TSMC developed wafer-on-wafer (WoW) fine-pitch bonding (< 10nm) using through silicon vias (TSVs) and InFO-on-substrate (InFO_OS) for HPC applications with large dies for logic, and to combine and logic and memory in a small form factor. The new InFO antenna-in-package (InFO AIP) will enable integration of antennas. Yu confirmed that InFO platforms are targeted at 5G designs. He explained important enhancements to CoWoS: 0.4µm L/S, C4 bump pitch down to 130µm and Interposer sizes up to 2X the reticle size (1660 mm2 ). Yu concluded his presentation with: “All these advanced packaging technologies demonstrate that TSMC is growing from an IC foundry to a system integration foundry.”

Dr. Kevin Zhang, VP Business Development, started his message with: 5G applications require not only very low power solutions but also a multitude of radios in the package. Zhang explained that 22 ULP is a 5% optical shrink of 28 HPC+ to simplify cost reductions. He announced that 22 MRAM and 22 RRAM will be released during 2018, ’19 and 2020.

Last, but not least, D. Cheng-Ming Lin, Director Automotive and MCU’s, described important trends in automotive: The need for cameras, Lidar, radar and ultrasound sensors to enable autonomous driving. In addition to the industry’s push towards fully autonomous driving, two other major demands challenge the industry: More green cars with zero CO2 emissions and, for electric vehicles, lower battery cost and shorter charging times. In addition to the evolution from safe to “smart” to “green” cars, Lin emphasized that TSMC is committed to qualifying 7nm technology for automotive applications. TSMC will support 48V electronics and up to 650V for powertrain components with BCD, GaN and even SiC.  Because product lifetimes in automotive are much longer than for PCs and smartphones, TSMC will keep these technologies in production for a long time.

In summary, this year’s TSMC Symposium demonstrated again that TSMC listens to market requirements, has the resources to analyze them and to act accordingly.

~ Herb