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 This year’s Roadmaps for Multi-Die Integration Symposium, hosted by MEPTEC on November 14, 2012 at the Biltmore Hotel in Santa Clara, CA, offered some interesting and different perspectives than the garden-variety 2.5D and 3D IC conferences of late. While there were a number of process-focused presentations, what I found most interesting were those that stuck to the symposium sub-topic of strategies and drivers, and looked beyond the silicon to address these technologies from the module and system perspective.

Own the profit; own the problem
One ongoing debate that seems to have everyone talking in circles is the combined discussion of supply chain business model and who owns the liability of the device. Harrison Chang, Ph.D, VP of Universal Scientific Industries, the module manufacturing division of ASE Group, offered a fairly elegant and simple solution, which he illustrated by showing iPhone teardown examples. “Who owns the multi-die integration?” he asked. “The die vendors? The module maker? The device owner? What about the gross margin? Who’s trademark will be stamped on the module?” Quite simply, whoever stands to gain the gross margin of the device owns the liability. This, explained Chang, allows for any business model to be used. Ultimately, the decision lies with the customer. (Rich Rice drove this point home further during his talk at the Known Good Die Symposium, which MEPTEC co-located with Multi-Die on November 15.) If your logo is on top of the package, than you procure the components and own it through the supply chain. With this as the ultimate guideline, there’s no reason that TSMC’s end-to-end approach won’t co-exist right along side the collaborative models being promoted by the other fabless, foundries, OSATS, IDMS and OEMS.

Reliability is an issue not to be ignored
Many have predicted that high-end servers in data storage centers will be the killer app for Wide I/O DRAM on Memory 3D ICs (think hybrid memory cube) because the cost isn’t as big an issue as it is with consumer products when you consider the performance improvements. This, we’ve been told, is how we will solve the bandwidth issue. But the hard truth is that until reliability is proven, 3D ICs are unlikely to be the solution for server applications.

Jan Vardaman talked about this in her presentation, Alternatives on the Road to 3D TSV. Still on her 3D IC “to do” list is a thermal design tool, proven reliability with the data to support it, and a sorted-out business infrastructure, which, in her words “has as much drama as a teenage girls sleepover.” (Now there’s something I can identify with!)

David Chapman of GSI Technology, manufacturer of high-performance memory, seconded the motion on the critical need for proven reliability. Chapman’s interest is in non-commodity memory in networking, because the tasks required of networking require more bandwidth. “All the techniques used to make commodity memory higher bandwidth just don’t work in the networking world.” he explained.

As much as we think reliability in our smartphones is critical, Chapman pointed out that in reality, smartphones are consumable products. Reliable servers are much more crucial, as that’s the place where all our smartphone data is stored. He even smashed his phone to smithereens right in front of us for added emphasis. But no worries, as soon as he picks up a replacement (assuming he purchased the insurance) his backed-up data will be restored. Device reliability, he explained, is especially critical for the high bandwidth memory (HBM) and networking applications that GSI targets, and at this point 3D ICs aren’t reliable enough to take that risk.

2.5D interposer is one solution, noted Chapman, but there’s a limitation with the reticle area because silicon substrates limit the maximum RAM compliment. “Organic interposers will be an interesting option once they have been fully developed and are available,” concluded Chapman.

Organically grown solutions
Chapman’s announcement must have been music to the ears of all the organic substrate manufacturers in the room. There were several companies represented offering solutions in the session, Emerging Technologies for Multi-die Packaging, including Unimicron Technology Corp, Kyocera America, and Samsung Electro-Mechanics.

Here are the key takeaways I got from listening to the speakers and during the panel discussion. On one hand, silicon interposers are very expensive, and organic interposers offer a balance between cost and performance. There’s a well-established infrastructure and supply chain, and we don’t have to start from scratch. However, it’s important to understand that organic interposers are limited to 5µm line and spacing. Anything lower is a function of silicon and not applicable. However, organic interposers show promise from performance and cost perspective to to fill a gap where coarse TSVs are required.

“Organic substrates are really promising, but its not here yet,” said Alex Tsai, TSMC North America. “What is here today is a qualified silicon interposer solution.” He was referring, of course, to TSMCs Chip on Wafer on Substrate (CoWoS) solution.

But can you test it?
During the panel, the topic turned to test. Steve Smith, of Synopsys, called test for 2.5D and 3D ICs a “new learning experience,” and that we’re still learning more about configurations being put into interposers and stacked die. He added that it’s all boiling down to a solution for memory built in self-test (BIST). “All the components are there,” he said. “The methodology is still being figured out.” Dave Love, of GenapSys, predicts that we are going to see more failures at the system level that didn’t show up at test. Joseph Dang at Kyocera said that organic interposers will be shipped 100% electrically tested.

Testing an interposer spurred some interesting dialogue. Does it need to be tested on both sides? It’s not a circuit, so how do you test it? Tsai said there’s no way to test every TSV and that in his experience at TSMC interposer yield is high. “We test to see if we can save cost not assembling bad die. ‘Pretty good die’ testing is very good.”  Vardaman noted that while lots of progress has been made in test areas, she doesn’t think there’s enough being communicated about it.

All this talk of test spilled over into the main focus’s of the next day’s symposium: Known Good Die: Reducing Costs through Yield Optimization. But that is another story for another day. ~ FvT

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