As part of the 3D tracks at both this year’s International Wafer Level Packaging Conference, held October 27-30 in Santa Clara, CA; and the 2009 IMAPS International Symposium, held Nov 3-5 in San Jose, CA, several suppliers offered up solutions addressing current limitations in via etch, insulation/barrier/seed layers, and fill process steps for 3D TSVs. By and large, the solutions presented shared a common goal: to follow a mainstream approach and reduce cost using existing technology. Most involved tool optimization, enabling process adaptations. Following are some suggested approaches.

Etch Processes
At Surface Technology Systems (STS), Chief Scientist Leslie Lea reports that both tool and process modifications are demonstrating favorable results for high etch rates with reduced scalloping and undercut, which results in better conformal coating and void-free filling. STS’s proprietary ASE processes improves upon standard Bosch process through a sequential 3 step process that is repeated until desired depth is achieved: 

  1. Deposit passivation layer
  2. Remove passivant from feature base
  3. Etch exposed silicon

Lea noted that to maintain or reduce sidewall roughness while increasing etch rate, it is necessary to reduce the cycle time by reducing the duration of each of the component steps. Therefore, to reduce passivation time, Lea recommends making it more efficient by changing the C4F8 plasma parameters and reducing substrate temperature. Additionally, the rate at which passivant is removed from the base of a feature should be maximized.

With regards to tool modifications, seeing the benefits of using a de-coupled vs conventional plasma tool (Increased plasma density, and greater flexibility to control ion and neutral radical fluxes), STS has addressed some of the drawbacks of conventional de-coupled plasma tool designs. Lea said by improving the power handling capability, making the plasma generation area larger, and adapting the source so that it generates good uniformity has resulted in a larger diameter via (50µm at 200 µm depth) or smaller diameter vias (2µm at 10µm depth). STS will announce more achievements in the coming months, notes Lea, related to high efficiency plasma sources, and the capability to perform both oxide and silicon etching in the same tool.

Brad Eaton, of Applied Materials (APMAT), presented the company’s alternative to the standard Bosch – or Time Multiplex Gas Modulation (TMGM) – etch process, that he said overcomes the limitations of scalloped edges and undercut issues that occur when high etch rates are attempted. According to Eaton, by multiplexing gas flow and RF power, the Applied TMGM process reduces the lateral etch while increasing vertical etch, resulting in smoother sidewalls.

In developing the Applied TMGM process, engineers eliminated the hard mask scheme, instead going with a resist mask process for high aspect ratio via. Additionally, APMAT’s SilVia etch tool, which has been optimized for TSV processes, is capable of performing an in situ oxide etch process to reduce the occurrence of undercut for subsequently easier insulation/barrier/seed layer steps. In summary, Eaton cited the benefits of this process as minimizing etch rate trade-off with respect to etch profile; elimination of costly mask schemes; a reduction in tool overhead by performing both the oxide and silicon etch steps in the same chamber; a 20-30% etch rate improvement, year over year; and cost of ownership (CoO) while preserving profile and depth uniformity.

Approaches to Insulation/Barrier/Seed metallization

Several suppliers addressed the issue of conformal coverage of high aspect ratio vias during the critical insulation/barrier/seed metallization steps.

Ajay Bhalnager Ph.D. Global Product manager for Applied Materials explained how subatomic chemical vapor deposition with tetraethyl orthosilicate (SACVD O3/ TEOS ) technology provides a highly conformal dielectric liner for high aspect ratio (HAR), front end of line TSV applications with a low cost of ownership that is scalable to enable 1µm film on the via sidewall. When it comes to the barrier/seed layers, Bhalnager noted that the broad scope of the TSV landscape (via first, last, interposer) requires customized solutions. With HAR via, the challenge of getting to the very bottom of the vias require high ionization of barrier seeds. Resputtering provides continuous sidewall coverage. Bhalnager recommended using titanium as the barrier metal to lower the TSV cost.

According to Stephen Golovato, of NEXX Systems, the company has developed a process called collimated PVD, which involves placing a grid between target and substrate to filters out shallow angle deposition, eliminating unwanted metal, with 20-30% of the metal reaching the wafer. Typically used up to aspect ratios of 5, this process helps to prevent over burden and pinch off at the top of the via. Golovato highlighted the advantages of collimated PVD, noting that it allows successful PVD architectures designed for advanced packaging to be extended to TSV seed processes. Well suited for CMOS image sensor TSVS and near-term 3D TSVs, it offers a cost effective solution for aspect ratios up to 5, as well as applicable for HAR, but at a reduced throughput.

Alex Wang, of Tango Systems, addressed via last approaches, focusing on dry Cu processes, and the challenges posed for step coverage of vias, in particular issues with side wall and bottom coverage. Wang noted that etch roughness is a significant challenge, as is scalloping, striation, and cornering.
Tango’s approach is to increase step coverage on side wall and also on bottom by implementing a long throw process on their systems to get material to bottom corners, a magnetic confinement to increase efficiency, and in-situ resputtering. Multiple positions in the same chamber allows for simultaneously re-sputter of materials. According to Wang, Tango has achieved 6:1 and 8:1 AR vias with this approach.

Via fill approaches

During his presentation on copper deposition for via fill, Erik Young, of Semitool explained how it’s all in the deposition process. “Copper electrochemical deposition is becoming the method of choice for via fill.” He noted. Void formation occurs when there is a higher deposition rate near the via mouth due to faster charges causing pinch-off. He recommended chemically reducing current crowding at the via mouth using a pulse reversed wave form. Semitool’s generation 3 process is a “super bottom-up” fill process that prevents voids from forming.

According to Yun Zhang of Enthone, the ideal fill is one that is complete with no voids, minimum overburden, and zero dimple. She said the best way to achieve this is by optimizing chemical systems along with the process, and that sometimes it involves the customer wafer to get it just right. It is critical maintain u-shape growth throughout process, driving as much of the copper as possible to the bottom keep the current higher on the side wall. It is also critical to maintain a steady-state plating bath. Zhang also noted that downstream processes such as CMP, wafer thinning, and subsequent “thermal excursion” processes are also critical to successful TSV formation.

In addition to providing technical solutions, Zhang voiced the general message that applies to the TSV supply chain as a whole. “Integrating Cu-TSV successfully in 3D stacking requires fundamental understanding of materials compatibility and reliability of the final package in its intended application environment. “ she states in her summary, therefore “Partnership (IDMs, design houses, materials suppliers, equipment suppliers, assembly houses) is key to gain such systematic and realistic understanding” of what is needed to succeed.

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