Soitec unleashes the Power of Three

A walk across the impressive Bernin, France campus that is home to two of Soitec Group’s three divisions takes you past three production-level fab facilities – aptly named Bernin 1, Bernin 2, and Bernin 3, plus a development facility. The company’s three-stage business model encompasses innovation, licensing, and production to allow for seamless transfer of full technology and process control to customers as a turnkey solution. The organization’s core competencies are also three-fold: Smart Cut technology used to manufacture high performance, energy efficient silicon-on-insulator (SOI) chips; Picogiga’s III-V technology for gallium nitride based wafers for high-frequency electronics; and most recently Tracit’s Smart Stacking process for low stress, low-temperature wafer-to-wafer bonding, planarization and cleaning (another 3). It seems only fitting that Soitec has recently unleashed its power of 3 on the 3D integration market: Thus the reason for my visit to Bernin.

As Bernard Aspar, Ph.D., managing director of Soitec’s Tracit business unit explained, the company’s 3D strategy relies on (you guessed it) 3 core technology pillars that clearly address needs in middle of the line processes for via last processes. Pillar 1 is the Smart Stacking oxide-oxide wafer bonding and thinning. Pillar 2 refers to low-temp Smart Cut technology for transferring thin layers, and Pillar 3, still in development in partnership with Leti, is metal-to-metal direct wafer bonding. (I got a glimpse of this the next day at Leti, and even initiated the molecular bond – very cool stuff.)

Although Aspar pointed out that Smart Stacking doesn’t always require SOI wafers, when this particular trifecta is performed using them, it is ideally suited for backside illumination (BSI) processes for next-generation CMOS image sensors, because the buried oxide layer acts as an etch step for wafer thinning while providing device backside protection. Additionally, the ultra-thin layer transfer of the Smart Cut processes allows for higher density TSVs.

Still, according to Jocelyne Wasselin-Suzan, Ph.D., VP of marketing and business development, although advantageous, the flexibility of being able to use SOI or bulk silicon isn’t the main reason Soitec Group initially brought Tracit’s service portfolio into the fold. What’s really being leveraged here is the opportunity to offer customers either an outsourced model or an in-house solution. What is unique to Soitec is that technology development is performed using production-level machines. An approach, notes Aspar, that allows for a quicker ramp to volume production using either Soitec’s established infrastructure for both 200 and 300mm wafers, or through a total technology transfer to the customer’s manufacturing lines.

Following our discussion, I was treated to a tour of Bernin fabs, where I got my first view of a fully equipped, class l cleanroom for fabrication of SOI wafers (from the outside) – where tools for thermal oxidation and implantation and cleaning were lined up and operating. Although I was unable to take photographs for security reasons, just walking through the viewing hall gave a bigger picture than simply going through a power point. A tour of the wafer bonding area of Bernin III followed, where Smart Stacking processes take place. One small detail that really drove home the production level of this facility was the careful attention to clean room protocol even outside the class-defined areas. Booties are worn throughout the facility to reduce particles. Cardinal sin is wearing uncovered street shoes anywhere past the reception area. And an obvious nod to the Grenoble region’s varied climate, as well as to avoid suiting up several times a day are the connecting hallways between Bernin I & 2. Seriously, these guys think of everything.

Soitec’s current focus in the 3D integration market has lead to partnerships with several key leaders in the industry, noted Aspar. The first partnership, announced last May, is with ST Microelectronics for the development of BSI for CIS targeting consumer applications. In Soitec, this business started few years ago for integrating the technology in high-end image sensor technologies for medical applications. Additionally, Soitec has joined in IBM’s 3D IC efforts to develop highly flexible and cost-effective wafer-to-wafer stacking processes leveraging its Smart Stacking technologies, including oxide-to-oxide and metal-to-metal molecular bonding. As the saying goes, good things happen in threes. When it comes to expanding into 3D markets, it looks like there’s two down and one to go.

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