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For me, SEMICON West involves a careful balance of attending sessions, keynotes and panels, combined with one-on-one interviews with thought leaders in 3D ICs, as well as manufacturing suppliers who have the onerous task of developing, promoting, and selling the next great solution for 2.5D and 3D IC manufacturing. Over...
Product Description Copper DBI® technology is a patented low cost, scalable process technology that was licensed for 3D memory assemblies in December 2012. Copper DBI® technology offers higher throughput and better scalability when compared to copper thermo-compression bonding. This technology can be incorporated into die-to-die, die-to-wafer and wafer-to-wafer processes. Testimonial...
Product Description The EVG850TB/DB XT temporary bonding/debonding platform addresses the high volume manufacturing needs for thin wafer processing. Nine process modules combined with integrated FOUP storage system allow true continuous mode of operation with an unprecedented throughput of >40 bonds/debonds per hour. The EVG850TB/DB XT supports all common bonding adhesives...
CoatsClean™ combines process, equipment and formulation technology to deliver innovative, low cost-of-ownership approach to single-wafer photoresist and residue removal ST. FLORIAN, Austria and INDIANAPOLIS, Ind., June 17, 2013—EV Group (EVG), a leading supplier of wafer bonding and lithography equipment, and Dynaloy, LLC, an international manufacturer of chemicals for the electronics...
For the 8th year in a row, I did NOT attend SEMICON Singapore. But apparently this is the year I should have been there to cover the 3D IC Forum, as it was well attended and had a robust program with 15 speakers and a panel discussion (at least that’s...
For me, the most exciting news so far at this year’s 3D ASIP conference has been the announcement that Tezzaron Semiconductor is licensing both Ziptronix’s Zibond and DBI technologies . Really, I did backflips when I read the press release, because I have a soft spot for technology innovators and...
There's no place like SEMICON West for a company to make a major announcement. After all, it is the semiconductor industry's annual 'coming out party'. My inbox was flooded with press releases this morning, and since my flight was delayed so much that I completely missed the SEMI press conference,...
This week’s webinar on chip stack assembly simulation, presented by Kamal Karimanal of Cielution offered some useful information on how modeling can be used to minimize warpage in 3D stacking. In 3D stacking, versus traditional flip chip processes, thickness of RDL layers in comparison with the thinned die or wafer can lead...
Coverage of the GSA Memory Conference continues in this week's issue of Chip Scale Review Tech Monthly. Francoise von Trapp contributed this article. While there continue to be incremental improvements and innovations in single chip packaging technologies, it’s nothing compared to the focus on multi-chip assembly and packaging technologies. Whether...
If your company is located in France, and/or is involved in micro and nanotechnologies for microelectronics, chances are it’s either a spin out of Leti, its parent organization CEA, or is closely tied in ongoing collaboration to this major European research center for applied electronics. At least that is...
