Matches for your search: "hybrid bonding "
SPTS Technologies has launched its low temperature plasma-enhanced chemical vapor deposition (PECVD) solution for via-reveal passivation in 3D-IC packaging applications. Already proven in 300mm volume production fabs, the Delta fxP® PECVD system deposits dielectric layers onto bonded substrates at wafer temperatures below 200°C, with throughputs up to twice that of...
Outsourced Semiconductor Assembly and Test (OSAT) provider, STATS ChipPAC Ltd., has announced qualification of its 300mm middle-end-of-line (MEOL) manufacturing operation for Through Silicon Via (TSV) capabilities, and will transition to low volume manufacturing. STATS ChipPAC says it is firmly engaged with multiple strategic customers on TSV development programs that support the...
The R&D centers were out in full force at this year’s SEMICON West, presenting on their latest activities in all areas of 3D technologies, from 3D transistors, to 3D ICS, to full-blown 3D Systems. I was able to attend a smattering of presentations at events hosted by imec, CEA-Leti, SEMATECH...
Georgia Tech’s Packaging Research Center, in its pioneering chip-last embedded interconnection technology, demonstrates World's Thinnest 3D Organic Package at 130um thickness at 30um interconnection pitch using ultra-short copper-copper interconnections and bonding below 200oC for highest electrical performance. The "Ultra-SLIM Packages have built-in vertical connections to the top surface
Repeat Order for IQ Aligner Further Solidifies EVG’s Position as Leading Microlens Molding Solutions Provider for Wafer-level Camera Applications St. Florian, AUSTRIA, March 27, 2012 – EV Group (EVG), a leading supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that Himax Technologies,...
To enable high-volume production readiness of 3D-based products, SEMATECH’s 3D Interconnect and Manufacturability programs will be conducting Equipment Maturity Assessments (EMAs) of several critical 3D tools during 2012 to establish functional equipment capabilities and address high volume manufacturing maturity issues. The assessment is a cooperative effort among experts from SEMATECH’s...
Keith Cooper, Technology and Development, SET North America reports from 2010 IMAPS International , where he attended the 3D Panel, “Roadmap, Technical and Business Progress of 3D Integration and Packaging”. At the recent IMAPS Annual Meeting in Raleigh, NC, a panel of 3D experts addressed a series of questions moderated...
Reporting progress for CEA-Léti was 3D program manager Mark Scannell, who notes an overall shift in what’s driving Léti's 3D developments.
SEMATECH, the Semiconductor Industry Association (SIA), and Semiconductor Research Corporation (SRC) announced today they have established a new 3D Enablement program to drive cohesive industry standardization efforts and technical specifications for heterogeneous 3D integration. Administered by SEMATECH’s 3D Interconnect program, based at the College of Nanoscale Science and Engineering (CNSE)
EV Group (EVG), supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, announced that it has developed a new micro-lens molding process that can enable volume production of very-high-resolution (up to eight megapixels and higher) wafer-level optics for use in smart phones, pico projectors and...
