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MRSI Mycronic, part of the Mycronic Group, will present advanced assembly solutions at the 26th China International Optoelectronic Exposition (CIOE) from September 10-12, 2025, in Shenzhen. With over 40 years of industry experience, MRSI Mycronic will highlight die bonding and active alignment solutions focused on precision, speed, and reliability for...
Meeting the Thermal Challenge of High-Performance Compute ICs The semiconductor industry is undergoing a major transformation, driven by the demand of artificial intelligence (AI) and high-performance computing (HPC). As processor chips become more powerful, they generate higher power densities, making thermal management a critical challenge -especially for data centers. These...
MRSI Mycronic is proud to announce the launch of the MRSI-LEAP high-speed 1µm die bonder. This innovative equipment is designed for ultra-high-volume manufacturing of optical modules, including Chip-on-Carrier (CoC), Chip-on-Submount (CoS), and Chip-on-Board (CoB) assemblies utilizing epoxy processes. The MRSI-LEAP high-speed 1µm die bonder boasts a range of innovative features...
The Lunar New Year is soon upon us, and we will be celebrating the Year of the Goat with firecrackers, red packets (I hope!), and the evening parade in San Francisco on 07 March 2015. The goat is a sturdy animal whose praises are often undersung. Undersung – that sounds...
New this year at SEMICON West, and just introduced to the program late last week, the Expert TechHUBs will help attendees find answers to specific semiconductor test and packaging questions. Meet with industry experts in an informal discussion group on the North Hall show floor at TechHUB Test or in...
It’s common knowledge among those working feverishly to bring 3D TSVs to market that one of the areas still being ironed out in the back-end-of-line processes is thin wafer handling.
Another early start (5:30am) to catch the train to Grenoble. The trains went on strike (a regularly scheduled occurrence) but lucky for me, the strike didn’t affect trains running before 8am. (I love France. They’re so civilized here…) As I wasn’t scheduled to meet with the team from Soitec until...
This week’s webinar on chip stack assembly simulation, presented by Kamal Karimanal of Cielution offered some useful information on how modeling can be used to minimize warpage in 3D stacking. In 3D stacking, versus traditional flip chip processes, thickness of RDL layers in comparison with the thinned die or wafer can lead...
EV Group (EVG) supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, announced the completion of its newly expanded cleanroom IV facility at its corporate headquarters in Austria. As part of the company's long-term growth strategy to address high-volume tool orders and speed time to...
This year’s 2010 IEEE International Interconnect Technology Conference (June 7-9, Burlingame, CA) has caught the 3D fever.
