Another early start (5:30am) to catch the train to Grenoble. The trains went on strike (a regularly scheduled occurrence) but lucky for me, the strike didn’t affect trains running before 8am. (I love France. They’re so civilized here…) As I wasn’t scheduled to meet with the team from Soitec until 2:30, I had a chance to squeeze in lunch with Yann Guillou, of ST Ericsson, the wireless arm of ST Microsystems. In addition to 3D developments at his company, Yann keeps me posted regularly on what’s happening in the design community with regards to 3D integration.
We’ve been hearing a lot lately about wireless applications being the next big driver of 3D integration, and according to Guillou, that is indeed the case at ST Ericsson. There’s a 3D pilot line up and running at the facility here in Grenoble. Unfortunately my schedule didn’t allow for a tour, but there’s always next time.
But today’s post is mainly about my visit to Soitec. When I mentioned to a colleague I was visiting Soitec on this visit, the response was “Soitec is doing 3D?” And the answer is yes, announced as of SEMICON West 2009, but they really got started a while ago. (It’s just not their way to announce what they’re doing until they’re already doing it.)
I really like the success story behind this company, as told to me by Camille Darnaud-Dufour, who’s been handling the marketing and PR for Soitec since they first spun out of Léti in 1992. As we walked across an impressive campus of 3 fabs and 1 development building plus ancillary office buildings, surrounded by the French Alps of Grenoble, she told me that all of this was founded by 2 Léti scientists (André-Jacques Auberton-Hervé and Jean-Michele Lamure) who had an idea for fabricating silicon-on-insulator (SOI) wafers, patented as Smart Cut technology, which offers higher performance than bulk silicon. To see how they have grown and expanded in such a short time should be an inspiration for any start-up with a novel idea.
The 3D integration involvement came with the acquisition of Tracit, another spin off of Léti founded by Dr. Bernard Aspar, who developed Smart Stacking, a wafer-to-wafer process that integrates direct wafer bonding and chemical and mechanical thinning of partially to fully processed device wafers into a single process step. This process is especially suited to manufacturing CMOS image sensors (CIS) with backside illumination, and can be done witheither bulk silicon or SOI wafers. Becoming a division of Soitec was beneficial because it provided what Tracit needed to become a full industry player and provide a full turnkey solution; namely a full production wafer fab. Besides the integration of the thinning process, another differentiator of Smart Stacking is that it’s developed on production level tools, allowing for faster ramp to high-volume production.
At Soitec, I got my first look at a class 1 clean room running full tilt, as well as the bonding operation in the 300mm fab. (I noticed quite a few EVG bonders lined up to do the job, which answered my question of what tools are being used to run the Smart Stacking process.) But by far, the highlight of the day was dinner with both Camille and Soitec CEO, Paul Boudre. Over a sumptuous meal in an old chateau perched high up the mountain, Boudre, picked my brain about the status of the 3D market, who’s doing what, and how Soitec can best position itself for growth. Certainly offering a cost-effective W2W process is a big step in the right direction.
It looks to me that we have another clear case of a disruptive technology forging its way through the sea of traditional approaches. It has occurred to me that all of these guys should form their own consortium to really shake things up. Who knows what could happen….
P.S. Stay tuned for full reports (including photos) for each company visited on this tour. These are just a few of the highlights along the way. On to Leti…. – F.v.T.