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NHanced Semiconductor president Robert Patti’s presentation at the recent SEMIEXPO Heartland in Indianapolis, IN described the critical role of advanced packaging in continuing the progress of Moore’s Law in semiconductor development. Following is a summary of his presentation. In Gordon Moore’s seminal paper, he predicted a ‘Day of Reckoning’ for...
3D InCites is excited to be the official industry partner of the 2025 IMAPS Device Packaging Conference (DPC) this March. With such a strong member presence this year, I’m looking forward to meeting so many of you during the course of the event! Taking place from March 3-6 in Phoenix...
Achieve higher integration density with collective die-to-wafer bonding Advanced packaging is currently facing a critical challenge to increase manufacturing efficiency without sacrificing device performance. Vertical integration techniques, such as multi-tier die stacking and hybrid bonding, enable increased integration density, therefore improving yield of high-quality devices. However, these highly precise processes...
Let’s continue our look at the key presentations at IMAPS DPC 2022 from ASE, Amkor, Yole Développement and Adeia. ASE Lihong Cao discussed ASE’s “Enhanced Fanout Embedded Bridge Packaging Technology for Chiplet Integration” The packaging industry is looking for alternatives to silicon through silicon via (TSV) technologies. Embedded SI die...
IMAPS DPC 2022 This year’s IMAPS Device Packaging Conference (DPC) was live once again, though most of the live attendees were from the US and far fewer were from Europe and Asia than usual. The unique aspect of this year’s meeting was certainly the Global Business Council session (GBC) which...
Major Foundry Investments in the US Samsung, Intel, and TSMC are all making large foundry investments in the US. First reported in May, Samsung Electronics is reportedly now close to finalizing the site selection for its new $17B foundry in the United States. The investment would create a second foundry,...
Temporary wafer bonding processes were initially developed for enabling three-dimensional (3D) stacked integrated circuits (ICs). For example, dies can be stacked on top of each other using die-to-wafer stacking to create 3D IC stacks. Through-Si vias (TSVs) and microbumps are used to interconnect the finished dies. These techniques require the...
The 2020 3D InCites Awards program has been a bit of a nail biter for us all, as we waited for the judges’ votes to see how they aligned with the online votes. Remember: the online votes serve as one judge. So, it was possible to win the online vote...
SEMICON West, San Francisco, Calif., July 10, 2012 — EV Group (EVG), a leading supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that its GEMINI® Automated Wafer Bonding System has become the first product to pass a systematic, rigorous Equipment Maturity Assessment...
SUSS MicroTec,supplier of equipment and process solutions for the semiconductor and related markets, launched the XBC300 Gen2, a high volume manufacturing platform for advanced 3D processing. The new bonding equipment can be used for permanent wafer bonding, or debonding and cleaning of 200mm and 300mm wafers. It is designed for...
