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Amazing breakthroughs lie ahead. It won’t be easy — but it will be awesome. How it started I remember when wafer-level stacking was brand new. It wasn’t “advanced packaging” back then. Even the term “3DIC” was brand new. The idea was audacious and stunning and we loved it. We seized...
Jean-Marie Brunet, Vice President and General Manager of the Siemens Hardware-Assisted Verification business unit finds himself and his group in a unique situation when it comes to the topic of chiplets. The group designs a chiplet for their own products and sells those products to verification engineers who are verifying...
The last month has been an interesting time in the world of sustainability. First, the SEC released its estimates on costs for reporting on climate change, and a document for review on suggested reporting standards. The S&P Dow Jones index removed Tesla from its top 10 ESG index, The Davos...
In the ESD Alliance line-up of Fall 2021 events, next is a webinar on export compliance, a topic that affects all companies in the 3D InCites community and semiconductor industry, not just the system design ecosystem as the title implies. The “Understanding Export Regulations Affecting the Electronic System Design Ecosystem”...
Shortly before the summer break started, I attended a number of industry conferences: MEPTEC, ECTC, DAC, MEMS & Sensors, ASME and SEMICON West. At all of them, I clearly noticed that our industry is looking beyond “Moore’s Law” to advanced IC packaging, multi-die ICs, and system scaling. However, at every...
What is heterogeneous integration, and is it my friend, or is it my foe? Why does it seem everywhere one looks, heterointegration is standing up and being counted right now, in mid-2015? And what kind of doors is heterogeneous integration opening for microelectronic technologies beyond, complementary to, or in competition...
A major concern in 3D IC designs is ensuring reliability and quality. Specifically, there is a growing need for design verification flows that can determine the cross-layer implications of the stresses caused by through silicon vias (TSVs) and chip-package interaction (CPI) induced mechanical stresses. Because 3D IC stacks have limited...
DesignCon’s 2015‘s tag-line “where the chip meets the board”, was a very appropriate message, and summarized in a few words a major trend in our semiconductor- and electronic systems industry: The increasing need for holistic planning as well as modeling of building blocks, not only for better up- and down-stream...
Good news! At last week’s GSA 3D IC Packaging Working Group Meeting, July 23, 2014, Jan Vardaman uttered the words I’ve been waiting to hear her say for quite some time. “Memory stacks with TSVs are here!” Vardaman cited three companies actively involved in new memory architectures, all of which...
Tuesday’s (July 15) Nightly Business Report surprised me with an – in my view – very important announcement: Apple and IBM are going to cooperate to offer enterprise solutions. See more about this significant step here and in many other headline news coming out this week. The former rivals are...
