Heterointegration, Friend or Foe: Opening the Door for Technologies Beyond Moore’s Law Silicon

Heterointegration, Friend or Foe: Opening the Door for Technologies Beyond Moore’s Law Silicon

What is heterogeneous integration, and is it my friend, or is it my foe?

Why does it seem everywhere one looks, heterointegration is standing up and being counted right now, in mid-2015?

And what kind of doors is heterogeneous integration opening for microelectronic technologies beyond, complementary to, or in competition with Moore’s Law silicon-based semiconductors?

Dr. Peter Ramm, Fraunhofer EMFT, writing in 3D InCites on January 16, 2015, noted that “There are certainly different understandings in the microelectronics community regarding the definition of heterogeneous 3D integration.”

According to Ramm, heterogeneous integration can be defined as the integration of different devices, such as a CMOS processor and a memory; heterointegration can also be defined as the integration of components with significantly different device technologies as e.g. CMOS and MEMS; and, finally, heterointegration can be defined as the integration of different substrate materials, e.g. GaAs / silicon.

From a materials integration perspective at the materials integration level it could also be InGaAs / silicon, or InP / silicon, the motivation say for use in high mobility transistors; or maybe it’s fully-formed III-V photonic components integrated with silicon logic, as IBM recently announced, and as was covered in the EETimes piece “IBM Demos CMOS Silicon Photonics.”

“’We’ve been doing silicon photonics research since 2000 because we understand all the opportunities they have for processing data. We believe our efforts will result in the first marketable chip to put CMOS and silicon photonics on the same chip,’ Supratik Guha, director of Physical Sciences, IBM Research told EE Times.”  “’The lasers are brought in from off-chip in order to be modulated, but eventually we hope to incorporate III-V lasers right on the chip,’ Will Green, manager of the Silicon Photonics Group at IBM Research … .”

Why the visible new posture for heterogeneous integration?  That’s possibly the result of the work being promoted by the ITRS Heterogeneous Integration Focus Team, as part of an ITRS 2.0 refresh.

Writing in Solid State Technology, the team says its mission is to “ … provide guidance to industry, academia and government to identify key technical challenges with sufficient lead time that they do not become roadblocks preventing the continued progress in electronics that is essential to the future growth of the industry and the realization of the promise of continued positive impact on mankind. The approach is to identify the requirements for heterogeneous integration in the electronics industry through 2030, determine the difficult challenges that must be overcome to meet these requirements and, where possible, identify potential solutions.”

About those difficult challenges, the ITRS heterointegration focus team thinks “The top‐level difficult challenges will be the reduction of power per function, cost per function and latency while continuing the improvements in performance, physical density and reliability. Historically, scaling of transistors has been the primary contributor to meeting required system level improvements. Heterogeneous integration must provide solutions to the non‐transistor infrastructure that replace the shortfall from the historical pace of progress we have enjoyed from scaling CMOS.”

Visibility for heterogeneous integration? When the ITRS talks people listen.

And when DARPA talks people listen too.

DARPA, which has possibly influenced the course of semiconductor technology more than any other single organization, is working again on the bleeding edge of technology (and raising heterointegration’s visibility) with its latest Heterogeneous Integration of III-Vs and Silicon project(s), aka Diverse Accessible Heterogeneous Integration, DAHI.

In a presentation made to CS International in March 2015, Dr. Daniel Green, program manager, Microsystems Technology Office, DARPA, related how DAHI is seeking to heterogeneously integrate InP HBTs, GaN HEMTs, and RF MEMS with sub-micron silicon CMOS to reach “unprecedented levels of performance (e.g. bandwidth, dynamic range, power consumption).”

In Dr. Green’s example, the heterointegration of III-V components with 130nm CMOS (trailing edge CMOS these days, and cheap) is expected to achieve the same kind of functional performance as a silicon device five process nodes further down the line (28nm; not so cheap).

That’s the kind of result that deserves to stand up and be counted, and is very much along the lines of what others are proposing – to repurpose trailing edge CMOS running on 200mm wafers in order to add new value.  (For more on this please see the piece “IoT Requires the Evolution of the “New” 200mm Fab.)”

Or is heterointegration’s new visibility the result of a current commercial success, success always being a convincing trophy to bring to any table?

Consider the Apple iPhone 6 and 6 Plus.  You may have received one for the holidays, or maybe someone you know did.

Apple shipped approximately 75M units of those phones in the fourth quarter of 2014; each phone has two camera modules, one front, one rear, and each of those camera modules contains a heterogeneously integrated CMOS Image Sensor.

“The Sony ISX014 8MP sensor features 1.12um pixels and integrated high speed ISP. The pixel layer and logic layer part are manufactured as separate chips and stacked by using TSVs. Previously the pixel and logic circuit of Sony’s back side illuminated (BSI) CMOS image sensor were formed during the same fabrication process.” (Dr. Phil Garrou, Solid State Technology.)

That’s 150M units of a 3D heterogeneously integrated component shipped into the consumer electronics market by one smartphone supplier in just one quarter.

Stand up and be counted.

Whether the camels’ nose has entered the tent, or whether there’s now a foot in the door, or whether we are now seeing the thin end of the wedge, Moore’s Law silicon semiconductor technology, with its increasing limitations (cost; benefits), will soon, if it has not already, find itself in a competition, or a coopetition, with heterogeneous integration.

According to the ITRS 2.0 team, “Overcoming these [Moore’s Law] limitations will require heterogeneous integration of different materials, different devices (logic, memory, sensors, RF, analog, etc.) and different technologies (electronics, photonics, plasmonics, MEMS and sensors). New materials, manufacturing equipment and processes will be required to accomplish this integration and overcome these limitations.”

Heterointegration’s impact will be in mobile products, in big data systems and in the cloud; and in biomedical products, green technology, and in the Internet of Things.

That’s called the future, and it’s heterointegration, friend or foe, opening the door.

From Pittsburgh, PA, thanks for reading.  ~PFW

[Editor’s Note:  This piece was originally published in the Summer 2015 MEPTEC Report.]