Paul Werbaneth

Paul Werbaneth is a long-time Contributing Editor at 3D InCites. Since entering the semiconductor industry…

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Chris Mack, “Gentleman Scientist,” published an excellent piece on March 30, 2015 in IEEE Spectrum on “The Multiple Lives of Moore’s Law – Why Gordon Moore’s grand prediction has endured for 50 years.”  (Hint: “hard work, human ingenuity, and the incentives of a free market.”)

Moore’s Law has several flavors beyond Gordon Moore’s prescient observation in 1965 that “integrated circuit density-doubling would occur every 24 months.” One flavor is that Moore’s Law is a law of economics, which goes for More than Moore as well. The other way to think about Moore’s Law is to think of it as an observation about performance, with that performance, for computing systems, for example. measured in FLOPS, or GigaFLOPS, or TeraFLOPS, or PetaFLOPS.

Squeezing more and more transistors into the same physical area of silicon means we will all have supercomputers in our pockets (great!), or be beholden to the Singularity (scary!) very soon. On the performance vector, besides continued transistor scaling, how else will we get to that bright, pocket supercomputer future?

“Via heterogeneous integration” is the answer I heard at the fifth annual CS International Conference, which was held in Frankfurt, Germany on 11 and 12 March 2015. (More on CS International 2015 here.)

The CS International 2015 talks that spoke most directly to compound semiconductor technology (think GaAs, InP, GaN, and InGaAs, for example) heterogeneously coming to the aid of Moore’s Law silicon and its continued progress were multiple.  Here are a few of my favorites, in the order in which the talks were presented.

Efficient Power ImageIn his talk on Ditching the Package to Drive Down GaN Transistor Costs, Alex Lidow, Efficient Power Conversion Corporation, presented his thinking that by implementing GaN-on silicon power devices it’s possible to get everything asked for on the world’s power switch wish list: lower on resistance; faster, smaller switches with lower thermal impedance; at lower cost, in a better package. And achieve a Moore’s Law revival in the process, thank you very much.

According to Alex, in the conclusion to his talk, “Gallium nitride has enabled smaller and faster power transistors. The elimination of all packaging has unleashed additional performance advantages due to reduced size, cost, parasitic inductance, thermal efficiency, reliability, and cost. For the first time in 60 years there is a technology that is both higher performance and lower cost than silicon!”

Give a talk like this at a compound semiconductor conference in Germany and the world takes notice: Lidow’s work was recently featured in a VentureBeat piece by Dean Takahashi, who boldly declares “Move over, silicon. Gallium nitride chips are taking over.” Dean’s been around Silicon Valley long enough to have basically seen it all, and if he’s excited by GaN’s prospects for augmenting or replacing silicon then I wouldn’t bet against him.

Mike Corbett, LINX Consulting, thinks there’s a firm place for III-V High Mobility Channels in Advanced Logic Devices & Foundries.  As he told us in his talk, when we look at the next few generations of technology beyond 16nm FinFETs, Mikes sees Ge fins entering High Volume Manufacturing at the 10nm process node, starting first at Intel.  After that, Mike expects that III-V materials will enter at Intel’s 7nm process node, with the foundries expected to be one generation behind this.

Why? “The industry hopes that high-mobility channels, made from Ge for pMOS and III-V materials for nMOS, will lead to faster devices that can also be configured to operate on lower power for mobile applications.” That’s why.
LINX Slide

In order to get there (realizing Ge/III-V MOSFETs on Si substrates) from here (plain vanilla 16nm) this needs to happen: the problems obtaining high quality Ge/III-V film formation on Si substrates need to be solved; gate insulator formation with superior MOS/MIS interface quality needs to be realized; low resistivity source/ drain (S/D) formation needs to be achieved; and total CMOS integration issues need to be worked out.

As Mike said, “High mobility heterointegration is not a drop-in process.” But the benefits will be significant.

Mike’s conclusions are that III-V high mobility channels will be coming to wafer foundries in ~7 or so years, somewhat behind their introduction at Intel; only a couple foundries will be capable of running III-V devices (TSMC is surely one, GLOBALFOUNDRIES one of the others, Samsung too, IMHO); wafers processed with high mobility FinFETs will cost ~60% more than state of the art foundry production wafers today; high mobility structures will represent the most expensive process blocks in the fab; but, after all that work, we can expect high mobility channels to have a long life in at Intel and in the foundries.

DARPA has possibly influenced the course of semiconductor technology more than any other single organization, certainly in the United States, and DARPA is again working on the bleeding edge with its Heterogeneous Integration of III-Vs and Silicon project(s), aka Diverse Accessible Heterogeneous Integration, DAHI, as presented by Dan Green.

DARPA DAHI ImageWhether it’s a matter of the “Best tech for the spec,” or the “Best junction for the function,” DAHI is seeking to heterogeneously integrate InP HBTs, GaN HEMTs, and RF MEMS with deep sub-micron Si CMOS to reach “unprecedented levels of performance (e.g. bandwidth, dynamic range, power consumption).”

Dan offered as an example the heterointegration of III-V components with 130nm CMOS, which is trailing edge CMOS these days, and cheap, in order to achieve the same kind of device performance as a silicon device five process nodes further down the line (28nm; not so cheap).

That’s pretty cool! DARPA is restoring the ability to choose the very best processes for a particular product or system without sacrificing cost.

The fourth talk of interest, and the one that gave me renewed hope for continued Moore’s Law progress that will extend through the rest of my career in semiconductors, came from Professor Jesus del Alamo, MIT, on III-V FETs for Future Logic Applications.

del Alamo SlideThe future can belong to InGaAs Trigate MOSFETS on silicon, in Prof. del Alamo’s view, or, even better, to Nanowire InGaAs MOSFETs, about which del Alamo says “Nanowire design is the ultimate scalable architecture.”

Moore’s Law, long may you run.  And you will, given a little hand from the heterointegration of III-V materials with silicon as we know it.

Is Moore’s law a ceiling, meaning we are confined by a roof on how fast our semiconductor device thinking and technology can progress?

I think the opposite, that Moore’s Law is really a floor, with the sky still the limit, reachable by hard work, human ingenuity, and the incentives of a free market.Magritte Sky

From Pittsburgh, PA, thanks again for reading. ~PFW