A major concern in 3D IC designs is ensuring reliability and quality. Specifically, there is a growing need for design verification flows that can determine the cross-layer implications of the stresses caused by through silicon vias (TSVs) and chip-package interaction (CPI) induced mechanical stresses. Because 3D IC stacks have limited access for characterization and measurement, yet have a strict known-good-die requirement, this type of analysis is crucial to getting an acceptable level of functional and parametric yield and reliability.
The ecosystem—including EDA companies, design houses, and fabs—is busily developing a design-for-manufacturability (DFM) and design-for-reliability (DFR) methodology for managing reliability threats in 3D TSV-based dies, stacks, and packages. In fact, I’ll be talking about just this topic at the Symposium on 3D Integration – Technology, Materials and Reliability on April 16. Dresden is lovely this time of year.
I’ll be discussing a set of physics-based compact models for a multi-scale simulation that assess the mechanical stress and temperature across the dies stacked and packaged with the 3D TSV technology. As an example, I describe how we account for the residual stress and temperature distributed in the back-end-of–line (BEOL) interconnect lines in the electromigration (EM) assessment.
There has not been much study given to EM issues in 3D stacked die, probably because of the belief that the current density in TSVs is smaller than in the BEOL interconnect segments, so EM failures should happen first in these segments. While this is true in general, die stacking can affect the degradation of the interconnect segments, creating a more complex picture of the stress distribution inside the dies mounted in a 3D IC stack. These non-uniform stress distributions generated by thermal ramps can be enough to cause failures even before an electric current is applied. On the other hand, when you add this stress to EM assessment, the critical stress can be developed faster, leading to failures that wouldn’t be detected by residual-stress-free EM analysis.
Another characteristic required for proper EM assessment of a 3D IC design is the temperature distribution across the interconnect. Therefore, to accurately estimate the risk of EM-induced failure, we need a full-chip EM assessment methodology that accounts for current densities, temperatures, and residual stresses in different interconnect segments for different workloads.
A Methodology for Thermal Analysis and Residual Stress Simulation
You can develop a thermal analysis flow that efficiently estimates the across-die temperature variation using a compact thermal model that represents a die as arrays of cuboidal thermal cells with effective local thermal properties. First, you divided all of the considered composite layers (BEOL, RDL, Si-TSV, bumps-underfill, etc) into a set of thermal cells and extract the effective thermal properties for each thermal cell in a layer. The effective thermal conductivities, which are functions of metal densities and routing directions of wires in each metal layer, are calculated based on the theory of effective thermal properties of anisotropic composite materials. Next, use the extracted thermal resistances/capacitances, estimated power sources, and thermal boundary conditions to generate a thermal netlist of the whole chip, where the nodal temperatures correspond to the nodal voltages and the powers correspond to the currents. Finally, calculate the temperature at each thermal node by electric solver. Figure. 1 demonstrates the calculated temperature distribution across the M1 metal layer of 32nm test chip.
You can use an existing multi-scale simulation methodology that assesses mechanical stresses in 3D IC dies, stacks and packages to extract residual stress across any metal layer of the on-chip interconnect. We propose a set of physics-based compact models for a multi-scale simulation to assess the mechanical stress and have developed a new calculation method, which is detailed in the technical paper I will present the Symposium on 3D Integration. Figure 2 shows the stacking-induced residual stress distribution across M1 layer.
Full-Chip, EM-Aware IR-Drop Analysis
EM-induced voltage drop in the chip power/ground grids is the most realistic cause of EM-induced chip failure. Indeed, EM-induced degradation of the resistances of individual wires exacerbates IR-drop, which can affect chip timing and signal integrity if it exceeds a specified threshold. So, EM-induced chip failure has a parametric rather than a catastrophic character, and is affected by residual stress and across-die temperature.
Our multi-scale simulation methodology for reliability assessment requires multi-scale materials data as input for the simulation. This multi-scale approach is of particular importance since for sub-micron, and particularly for sub-100nm, the materials properties are changing. The industry needs to conduct in-situ experiments to study the time-dependent degradation of interconnects in 3D ICs and to understand the reliability-limiting processes in microelectronic products and to proof physics-based models. Tomography experiments (3D) combined with the time-dependence 4D experiments, and particularly 4D microscopy, is the best possible approach. X-ray tomography and electron tomography are two experimental techniques that are applied within the 4D microscopy approach. The generation of a database for multi-scale material parameters of wafer-level and package-level structures is a practical approach to providing a set of data to the chip design community. ~ V.S.