Let’s start with the indoor rainstorm. I arrived at the Swan and Dolphin in Orlando just in time for the fan-out plenary session of ECTC 2017, so tossed my stuff in my room and headed on in (wearing jeans, no less!) You can read about that here. Afterward, I had a bite to eat with industry colleagues. Back in my room at 11:15 to call it a night, only to find it raining ON my bed thanks to a leak in the ceiling. 45 minutes later, a bellman arrived to move me to my “upgraded” room, where I was serenaded through the connecting door by my coughing neighbor. (Yeah, not a good start. I’m really glad this event only takes place every three years at this venue! But the food was great, I’ll give them that!)

Fortunately, ECTC’s program and the number of key semiconductor industry people it draws makes it a not-to-be-missed event, regardless of the venue. There is always so much content, both technical and market trend focused, not to mention all the exhibitors, that I always struggle with how to divide my time at ECTC. Thank goodness, this year I had Herb Reiter, eda2asic, as my wingman. We divided and conquered. He tackled the sessions and tutorials (blog coming soon) and I focused on the keynote and plenary sessions, the Technology Corner, and catching up with people about what they’ve been working on since last year. I was also promoting this year’s upcoming 3D InCites Awards (get your nominations in soon!) We captured some cool moments in photos here.  Read on for my takeaways.

Welcome to the Party, Intel!
What interested me the most about this year’s Luncheon Keynote, delivered by Babak Sabi, Corporate Vice President and Director of Assembly and Test Technology Development, Intel Corporation, wasn’t so much what was being said, but who was saying it. See if any of this sounds familiar:

  • Data is driving the industry, but it is worthless unless it ls processed and used and turned into information.
  • Advanced systems require high bandwidth and lower power “data pipes” which is only available through heterogeneous integration.
  • System designers raise the bar for overall performance.
  • On-package heterogeneous integration is critical.
  • We need to be able to integrate multiple nodes of Si.
  • Traditional packaging is limited in line/space. We need to move to next-generation packaging to get a “really wide pipeline” that can run at lower frequency, which is important for system power (High-density fan-out, anyone?).
  • Package scaling must keep up with silicon scaling and that means smaller pitch bumps. (FYI – imec has that one covered.)
  • We need to invent a new solution for multi-chip packaging (you mean like Amkor’s Big Five advanced system-in-package solutions and ASE’s advanced SiP modules, to name a few. Seriously, has this guy NEVER read 3D InCites?)
  • In the future (future?) packaging will become more wafer fab-like.
  • The industry needs to modify equipment that was originally built for silicon so that it can be used for wafer-level packaging at an affordable cost. (Hello? EV Group, SUSS MicroTec, SPTS Technologies, Tel-Nexx Systems, Ultratech, UnitySC, Rudolph Technologies, have been doing this for years.)

None of this is new. What is new is that it’s now being acknowledged as the path forward by Intel. Finally.

Brewer Science makes Headway in Temporary Bond/Debond
I chatted with Kim Arnold, executive director of wafer level packaging, who offered some highlights on the three papers they presented – two in conjunction with research institutes ITRI and imec.

The work performed in collaboration with ITRI demonstrated substrate support solutions for RDL-first fan-out processes (aka TSV-less interconnect), based on Brewer’s newly developed laser release layer technology. Arnold explained that since RDL-first involves a build-up process on (in this case) a glass carrier wafer, there is no temporary bond step, but only a debond from the carrier once the build-up is complete. To this end, the company has developed a laser release material that adheres well to both the glass and the titanium material that is used for the RDL build-up process. The material is applied to the carrier, the RDL build up is performed, followed by die-attach and overmold. They whole thing is flipped over and a short-wave UV laser is used to release the carrier from device wafer (Fig 1).

Figure one: RDL-first process flow.

As if a single temporary bond/debond (TB/DB) process hasn’t been difficult enough to achieve, in Brewer’s paper with imec, they’ve kicked it up a notch by demonstrating a double carrier process so that once a 28nm FinFet TSV wafer has been thinned to 5µm, it can be transferred to a second carrier and mechanically debonded from the first to expose the front side of the wafer for electrical performance testing. Two different TB/DB approaches, chemical and mechanical debond, featuring different Brewer Science material sets were used to achieve this.

“This is pretty exciting for us,” said Arnold. “We had to achieve and ultra-thin 2µm total thickness variation across the wafer with our material to allow for thinning.”

The third paper presented by Brewer provided an overview of the different approaches to FOWLP technologies, which ones need support wafer systems as part of the process flow, and how to select the right TB/DB bond and release layer materials to achieve the best results in each. A version of that article will be available soon on the 3D InCites Knowledge Portal.

GlobalFoundries Cracks the Memory on Logic Stack
Luke England, GlobalFoundries, had some exciting “industry first” news to share. His team’s latest achievement is the development of a fully-qualified chip-package interaction device comprising a 14nm logic die with 5×50µm Cu filled through silicon vias (TSVs), upon which two 14nm test chips that emulate high bandwidth memory (HBM) are stacked. The bottom die is connected to the board with C4 interconnects, and the bottom die to the top die use µm pillar interconnects.

What’s most significant about this device is that it has overcome the thermal management issue that has plagued 3D memory on logic stacks. This configuration allows for thermal cycle testing by reading the macros from the top die. The key to keeping the device cool is a conformal lid that was designed to have direct contact with the edge of bottom logic die, where high power content generates a lot of heat. This creates a direct path for the heat to travel from the bottom die up and out into the lid. He called it a “thermally-conscious design” because it was laid out purposely so that high power processing cores are not positioned right under the memory.

Not New but New To Me
On a stroll through the exhibitor booths, I saw John Lannon and Dean Malta, who were sporting Micross shirts, and dimly recalled Alan Huffman wearing a similar one at IMAPS DPC. Last I knew they all worked for RTI International’s Microsystem Integration and Packaging (“MIP”) Group.  I stopped in the Micross booth to check it out, and the conversation I had with Huffman slowly came back to me: I had missed the memo. Last fall, their division had been acquired by Micross Components to form its Advanced Interconnect Technology division.  According to the press release, “the merger brings together MIP’s value-added semiconductor processing techniques, including wafer bumping, 2.5D/3D packaging and interconnects plus novel sensor and thermal management devices, with the global hi-reliability electronics platform of Micross Components. But Lannon, Malta, and Huffman didn’t have to change much more than their shirts for this new job.  Micross also acquired the MIPs facilities, so the commute to work is the same. Still, going from and R&D organization to a commercial supplier is a big change. I look forward to learning more about this company.

New in Process Control
UnitySC filled me in on their most recent inspection platform targeting heterogeneous integration, the 4See Series, an all-surface wafer inspection system designed as a completed solution for 2D and 3D optical and edge inspection. According to Unity’s Gilles Fresquet, it’s the only inspection platform that can be configured to inspect all around and through the wafer. The platform features a deflector module that uses phase shift deflectometry for wafer surface inspection, an edge and line-scan modules that rely on confocal chromatic technology.

Because it’s modular, it can be configured based on application needs including application wafer thinning, µbumping, MEMS, and more. For fan-out wafer level packaging, Fresquet said it provides a high throughput solution for die placement, inspecting the positioning, rotation, and z-position of a die after being picked and placed on the carrier in a chips-first approach.

Hybrid bonding processes, which are another hot topic for 3D IC stacking with or without TSVs, is a target application for another tool in the UnitySC metrology and inspection toolbox:  NST platform (stands for nanoscale surface topography) tools. Fresquet believes its high throughput profilometry technology will fill a need for making sure that the hybrid bonds are good bonds.

But Wait, There’s More!
Still to come from ECTC 2017: a look at what’s happening in autonomous vehicles, and Herb Reiter’s report from the technology sessions. By the way, If you’re experiencing FOMO (fear of missing out) after reading this article and want to be included in the next 3D InCites event round up, schedule a briefing! You can catch Herb at the end of this month at the IMAPS SiP Summit in Napa, or at DAC in San Diego.  If you want to get on my calendar for SEMICON West, drop me a line.  ~ Françoise

Francoise von Trapp

They call me the “Queen of 3D” because I have been following the course of…

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