GSA 3D IC Working Group Looks at 3D IC Readiness from Design through Manufacturing

GSA 3D IC Working Group Looks at 3D IC Readiness from Design through Manufacturing

At the recent GSA 3D IC Working Group Meeting (October 22, 2014), where speakers from BroadPak, Amkor, and Invensas presented on 3D IC readiness, I was struck by three observations. First of all, while challenges to 3D commercialization still remain, but they’ve shifted from manufacturing challenges to design and infrastructure challenges. Secondly, high volume manufacturing (HVM) means different things to different people. Lastly, the semiconductor manufacturing giants and their partners aren’t hung up on technology challenges, and are the most confident that not only is the future is bright for 3D, its not about the future any more.

Meeting Design Challenges for 3D integration
Defining BroadPak as a “2.5D/3D integrator” that provides total solutions from design through manufacturing; Farhang Yazdani addressed the challenges of designing in 2.5D and 3D. “The most important decision is whether to go with via first, middle, or last,” he said. “That decision will affect your yield.” He explained that compared to circuit elements, TSVs are huge. Therefore, TSV count, placement and location is all crucial. Design for manufacturability is key. He talked about the impact TSV placement has on reliability, showing examples of uniform vs. non-uniform TSV patterns. In manufacturing, he said designs also have to address warpage.

“To achieve your goals, you have to have the right toolset,” said Yazdani. He described a 2D scenario, where the package ball-out is fixed, defined by the customer; the IC design team has frozen the die bump/pad pattern, and you end up with an expensive package substrate; in some cases the package could cost more than the die it contains. He said the reason for this is because the IC design, package design, and PCB design is done by different teams, and in the case of IC and PCB, different industries altogether. Package design and PCB design have semi-similar industries. This over-the-wall approach to design causes gaps that are unacceptable to 3D integration.

3D requires total system connectivity to close the gap and provide end-to-end connectivity, he explained. Part of this involves a single database to address ultra-dense connectivity across the system. “A high-level 2.5D and 3D flow requires intelligent path finding, which is a method for optimal integration of components and systems.” He said, noting that path finding is emerging as an area of expertise due to the ultra-dense connectivity, and that path finding and partitioning are coupled.

According to Yazdani, the tools and methodologies that address this area are here, albeit at different levels of readiness. Logical and physical co-design is ready. Analyisis tools for multi-physics co-simulation are available but need work. Co-design for test is here. Co-design for yield and reliability, as well as for cost, still needs work. Verification tools are ready.

How do you define HVM?
At the last GSA Working Group meeting, Jan Vardaman, Techsearch International, Inc. presented her Gap Analysis report, and commented that with 3 major memory manufactures announcing production of stacked memory devices using TSVs; that was what she called HVM. In Charles Woychik’s, Invensas, 3D IC readiness report yesterday, he said HVM was something quite different.

Part of answering the HVM question involves getting the 2.5D and 3D nomenclature right, he said. “We’re seeing memory stacking, and logic and memory stacking.” He said. “But really 3D monolithic IC is what you want to do, and that’s going to take awhile.”

3D IC Readiness

Figure 1: Where Invensas places 3D IC on the adoption curve.

He doesn’t consider 100M units to be high volume – and that to really qualify as HVM, 3D ICs need to be produced in billions of units a year. “The goal is to bring this technology to the mobile market. How do we do this at 400 units per second?” he said. The key, he says, is to take packaging knowledge and apply it to the 3D integration space – something Invensas refers to as “interconnectology.” This requires integrating the packaging world into the fab world to develop processes that will achieve huge volumes to bring the cost down and make the technology available to the mobile market.

He showed two Invensas 3D test vehicles. TV 3 is based on a chip-to-chip assembly-centric flow that uses solder-capped Cu pillars, for the OSAT world. TV4 is a chip-to-wafer fab-centric flow that uses Cu-Cu direct bond, targeting the foundry world. From the company’s perspective, they still are working to solve challenges in temporary bond, backside processing for a low-temp oxide bond, and wafer bump/debond and dicing.

Paul Silvestri, Amkor, painted a much brighter picture in his definition of HVM. During his presentation that focused on product status at Amkor and industry highlights, he said with confidence that 3D production capability is firmly at the memory suppliers. “There are a significant enough number of wafers being manufactured to consider it to be in production,” he said.

Silvestri explained about the variety of memory stack applications, most of which use die-to-die stacking for memory on memory or memory on logic chip-scale package applications. The hybrid memory cube (HMC) is the only memory solution with TSV logic integration. High Bandwidth Memory (HBM) is a DRAM solution with a logic layer as part of the DRAM process.

He also reported that Amkor “does NOT have any issues with wafer bonding and debonding due to the toolset vendors hearing the issues and working them out. “It’s been a year since we’ve seen that issue.”

As the technology is now robust, barriers to adoption have more to do with adapting the business model than anything. In the case of logic, TSVs are not a priority with suppliers, says Silvestri. There are still thermal challenges with thin logic die under memory stacks. TSVs add complexity to back-end-of-line (BEOL) processes, and are difficult to integrate.

With regard to the company’s interposer production status, Silvestri reported Amkor is receiving interposer wafers from two major sources and are engaged with two other supply customers with 2.5D wafers, in addition to one stand-alone company that supplies interposers for consumption within its own organization. It’s interesting to note that through working with these varied suppliers, TSV technologies have converged on similar looking TSVs with similar integration schemes. “This helps with the cost structure,” said Silvestri. “We don’t have to come up with different process flows.”

He says he expects 2014 to be a key year for transition from low to HVM for memory products. Currently less than 1% of all memory starts will be TSV specific products. He attributed this to the number of low cost bits still available, and that it will take a couple years to absorb that. While HBM and HMC are clearly kicking off, LLPDDR 3 and LLPDDR 4 are experiencing delays in TSV adoption due to the technologies’ ability to evolve, thereby pushing out the need for Wide I/O applications. “It’s often difficult to supplant the incumbent, noted Silvestri.

Figure 2: Amkor's TSV product roadmap. (courtesy of Amkor)

Figure 2: Amkor’s TSV product roadmap. (courtesy of Amkor)

Amkor has a 300mm TSV line installed and ready to go. They’re running wafers on a regular basis with better than 96% assembly yield, and that the issues aren’t really about yield, but about defect density. Essentially, Silvestri said that TSV wafer processing is robust and stable, and he doesn’t see show stoppers with the technology. “The TSV industry is ready for prime time,” he said, “We’re ready to support customers with product needs as soon as the roadmaps are updated.” ~ F.v.T.