A Path Finding Based SI Design Methodology for 3D Integration

3D integration is being touted as the next semiconductor revolution by industry. 3D integration involves the use of various interconnects that include balls, pillars, bond wires, through silicon vias (TSV) and redistribution layers (RDL) for enabling chip stacking, interposer and printed circuit board (PCB) based technologies. More recently 2.5D integration using silicon interposers has gained momentum as a viable solution for 3D integration. For such new integration schemes to be viable, mixing and matching of technologies is required to evaluate system performance early in the design cycle. The role of path finding is therefore to enable early exploration (planning) prior to costly implementation. Path finding must be based on an efficient electromagnetic analysis (EM) methodology which offers a good balance between speed and accuracy. In this work a hybrid solver is used which combines the Method of Moments (MoM) technique with specialized basis functions and the Partial Element Equivalent Circuit (PEEC) method to accurately provide design guidance.

Three types of test cases are used to explore key implementation areas. The impact of local interconnection density and routing topology for a 2 or 3 layer low cost Silicon interposer technology is investigated. Eleven signal lines are routed within a PWR/GND mesh grid for this example where the line width and spacing is varied to determine the variation in performance. A 49 TSV array is implemented in order to analyze near-end crosstalk (NEXT) between various TSVs in the array. The TSV array is varied to determine the crosstalk impact to determine where signals can be assigned. Wirebonds in a PoP (Package on Package) structure are designed to analyze the effect of design variations on performance. It is predicted that classical PCB designs for consumer electronic devices will continue to shrink as PoP implementations prove more advantageous for speed, area, power and weight related issues. The interconnect length and other parameters of the bond wires is varied to determine the impact on SI performance metrics.Various configurations of the wire bond structure have been demonstrated.

While several variations for each of the test cases described above is analyzed to determine the impact on signal integrity and performance, a larger parameter set can be explored using a Design of Experiments (DoE) methodology, which is not covered in this paper. From these findings, a set of rules can be created for detailed implementation. The examples covered show the attractiveness of using an exploratory tool early in the design cycle.

Download the white paper, A Path Finding Based SI Design Methodology for 3D Integration

(Republished with permission of the authors Bill Martin, E-System Design; KiJin Han, School of ECE, UNIST, S. Korea;  and Madhavan Swaminathan, Georgia Institute of Technology, Atlanta, GA, USA)