Every once in a while, it’s helpful to step back and get a broad view of what’s going on in the world of packaging as a whole to get a better idea of how much impact 3D has. In this morning’s opening keynote at the IMAPS Device Packaging Conference, Prismark Partners’ Brandon Prior did just that; offering a comprehensive snapshot of the 3D packaging landscape.
Reality check: the majority of packages in production today are still of the standard surface mount variety. According to Prior, advanced packaging is just on the verge of becoming a significant portion of the market. Flip chip and 3D configurations are starting to grab a significant portion of the value add, and he said 3D TSV would be the next evolution – or depending on who you talk to, revolution – in packaging approaches.
With regard to TSV adoptions, Prior’s remarks were made in the context of 3D packaging configurations, not to be confused with 3D silicon. In this case, competitive alternatives to TSV such as wire bond and flip chip are already well entrenched incumbent technologies and are therefore more readily used and available.
As it stands today, Prior notes that stacked die packages using wire bond interconnect represents 15% of the market today. Billions of packages are shipped that consist mainly of memory. One example of this is Toshiba’s nine die wirebond stack.
Next comes package-on-package (PoP) that are shipping in hundreds of millions. Prior said this is because it’s a much better approach for combining logic and memory as packages are tested separately before final assembly. Newer generation PoP configurations, such as Tessera’s µPilr and Amkor’s TMV PoP, offer improvements in height and number of die per package.
Embedded die in PCB configurations have been in limited production since 2005 noted Prior but have recently experienced renewed interest, particularly with the development of Infineon’s eWLB package.
TSV technology, considered to enable the ultimate system-in-package (SiP) in terms of performance, is only in production to date in non-3D structures such as CMOS image sensors, (CIS) and interposer technologies. However Prior predicts that over the next 3-5 years, performance improvement and size reduction will drive adoption of 3D TSVs.
With projects in the works such as RF, MEMS integration, we can expect to see the evolution of TSV technologies from SiP and TSV WLP to a true 3D stack. He cited early production examples of wafer cap processes or carrier die with TSVs such as AVAGO’s FBAR, EPCOS MEMS microphone; image sensor applications like Toshiba’s VGA module and next generation image sensor/logic module; and finally Samsung’s four die DRAM stack using TSV.
The main players driving development of 3D TSV logic/memory include Intel, IBM, AMD, and NVIDIA. Additionally, driving mobile applications are TI, Infineon, Qualcomm, Samsung, Sony, Toshiba and NEC and ST Microelectronics.
As of 2009 according to Prior, stacked die accounted for 15% of die area, about 5B packages; 0.2B packages are in POP/PiP configurations. Fan-out and embedded die technologies were still in early production with limited infrastructure, and TSV wa in production, but not in 3D.
By 2014, Prior predicts a shift in the landsape with stacked die reduced to 7% CAAGR; POP/PiP capturing 25% CAAGR; fan-out and embedded die experiencing success in select segments and companies; and in the 3D TSV realm, DRAM will be driving high volume manufacturing and logic/memory will be driven by portable devices.
What the industry needs to achieve this are equipment standards; viable processes for via creation, filling and handling; and solutions for power delivery and thermal management. Additionally, reliability concerns need to be addressed, infrastructure needs to be developed, and testing needs to be addressed.
If all goes well, Prior predicts the 3D implementation roadmap will look something like this:
- 2011-2013: volume production of via last, early adoption of via-first (via mid); TSVs in DRAM; and face-to face bonds without TSV will be in production.
- 2014-2017: volume production of via-first (via mid), DRAM, wafer-to-wafer processes, and MPU/memory stacks using die-to wafer-processes.