via reveal

Having the Courage to Design in 3D TSVs

Having the Courage to Design in 3D TSVs

I don’t know why it still surprises me to read conflicting reports on the progress of 3D TSVs. But I think Ron Huemoeller, Amkor, finally hit on it in his closing remarks during today’s webcast, “TSV Packaging at the Tipping Point”, moderated by Pete Singer, Solid StateTechnology/Extension Media. Huemoeller’s presentation and that of David Butler, SPTS, once again reinforced wha... »

SPTS: Blanket Silicon Etch Process for Via Reveal

SPTS: Blanket Silicon Etch Process for Via Reveal

The blanket silicon etch process performed on the SPTS Rapier XE achieves an etch rate >8.5µm/min, high selectivity (Si:SiO>150:1), and is ~3-4x faster than competing systems. A unique dual plasma source design creates a uniform etch (<±3%) across a 300mm wafer, which can be “tuned” to compensate for variations in in-coming wafer thicknesses. Testimonial Via reveal is a 2.5D/3D tec... »

SSEC: WaferEtch TSV Revealer

SSEC: WaferEtch TSV Revealer

SSEC’s WaferEtch™ TSV Revealer is a single wafer wet processing platform for 3D IC and interposer wet etching applications designed to reduce processing and capital equipment costs. The WaferEtch features superior uniformity of silicon thickness (as low as -/+ 0.7%). Testimonial Via reveal is a critical process step in 2.5D and 3D IC technologies that involves thinning the backside of the wafe... »

SPTS Technologies Announces the Omega® Rapier XE System for 300mm Wafer Silicon Etch Processing

SPTS Technologies Announces the Omega® Rapier XE System for 300mm Wafer Silicon Etch Processing

Newport, United Kingdom, 22 May, 2014 – SPTS Technologies, a supplier of advanced wafer processing solutions for the global semiconductor industry and related markets, today announced the launch of its Rapier XE system for 300mm wafer silicon etch processing. The new module offers significant advantages over competing systems as well as improved etch rate over the 1st generation Rapier in applic... »

Process Improvements Target 3D IC Cost of Ownership

Process Improvements Target 3D IC Cost of Ownership

Customers have asked and suppliers are listening. One sign of progress from last year to this year at SEMICON Singapore’s 3D IC Forum was the number of supplier presentations focused on process improvements that have been developed to lower the 3D IC cost of ownership (CoO). In addition to the cost-effective implementation of interposer technologies being worked on at Singapore’s A*STAR Instit... »

3D Wafer Level Packaging: Outlook for 2014

3D Wafer Level Packaging: Outlook for 2014

In 2013, SPTS equipment sales into the advanced packaging market grew by 75%.  Some of this was due to a resurgence in 3D wafer level packaging (3D WLP); the first-generation 3D that started with CMOS image sensors in the middle of the last decade. This year’s growth was predominantly due to the demand for fingerprint sensors first seen in the iPhone 5S;  next to be used in competing phones an... »

SSEC Introduces WaferEtch and WaferStorm Platforms to its Portfolio of Single Wafer Wet Processing Solutions at SEMICON West 2013

SSEC Introduces WaferEtch and WaferStorm Platforms to its Portfolio of Single Wafer Wet Processing Solutions at SEMICON West 2013

Unique Configurations Bring Improved Process Control, Lower CoO, and Higher Throughput to Pave the Way for Leading-Edge Technology Adoption Horsham, PA, (July 8, 2013) – Today at SEMICON West, Solid State Equipment LLC (DBA SSEC), a leading provider of single wafer wet processing systems used in the manufacture of semiconductor devices, high-brightness LEDs, and hard disc drives, announced t... »

3D TSV Summiit

European 3D TSV Summit: Focus on Cost of Ownership

Now that the “technology bricks” for building 2.5D devices and 3D ICs have been essentially qualified, the focus has turned to optimizing them for improved cost of ownership (CoO).  At last week’s European 3D TSV Summit, in Grenoble, France, many of the supplier presentations demonstrated how their companies have been working to optimize qualified 3D TSV technologies across the process flow... »