3D Wafer Level Packaging: Outlook for 2014

3D Wafer Level Packaging: Outlook for 2014

In 2013, SPTS equipment sales into the advanced packaging market grew by 75%.  Some of this was due to a resurgence in 3D wafer level packaging (3D WLP); the first-generation 3D that started with CMOS image sensors in the middle of the last decade. This year’s growth was predominantly due to the demand for fingerprint sensors first seen in the iPhone 5S;  next to be used in competing phones and other security-sensitive devices. That, together with more cameras in automotive means that 3D WLP will continue to be the largest volume TSV application in the near term.

2013 also saw the start of via-last TSV production on 200mm for MEMS and other small package devices. OSATS took completed MEMS devices from the IDM and etched TSV’s from the backside of the wafer. These packaged parts are yielding at levels equal or better than their wire bonded equivalent but provides the added benefit of smaller footprint. This progress implies that device manufacturers and packaging partners have worked out at least some of the long-standing concerns over shared IP and die testing – a significant step as we approach the era of 3D packaging of multiple die.

At the ECTC conference in May 2013, we presented work on dielectric stack engineering for wafer backside applications.  Low level production has started on 2.5D interposers, but one technical challenge is warpage of large area Si interposers. During the bump reflow step the die can distort by some microns meaning failed bump connections from die to substrate.  To address this problem, SPTS and our partners are developing stress compensation dielectric stacks on the die backside, using our low temperature TEOS oxide and nitride processes.

At the 3D Architecture for Semiconductor Integration and Packaging (3DASIP) conference in December, Eric Beyne of IMEC said that the backside processing steps were more demanding than the TSV formation on the device side. Eric believes TTV needs to be controlled to <2µm, and the vias revealed to 2 to 3µm.  If that can be maintained, he said, the need for costly CMP can be avoided.  SPTS has been leading the way in backside cost control through our unique ReVia™ endpoint system that detects the via tips as they emerge from the Si surface.   Simple timed etching cannot provide the level of control needed.  ReVia automatically compensates for any variation in Si overburden, giving consistent via heights wafer to wafer.

In 2014, we will see 3D WLP leaders move to 300mm wafers, and an increase in low I/O devices packaged with via-last TSV.  We will take a big step towards 3D high volume manufacturing (HVM) with the introduction of the stacked memory cubes for high bandwidth applications.  Beyond that, technical and economic challenges need to be solved in order to make TSV the industry standard packaging method.  At SEMICON Europa 2013, SPTS COO Kevin Crofton called for deeper relationships between the fabs and equipment makers. By adopting a more open working model with equipment vendors and leveraging their knowledge, we believe that the time to HVM can be reduced. ~ D.B.