The nominees for the 2020 3D InCites Awards are listed below by category.
Design Tool Provider of the Year
Coventor, a Lam Research Company - SEMulator 3D
Much of the $2-4B spent on developing a new semiconductor technology is in the form of iterative trial-and-error cycles of learning, conducted with many wafer-based experiments in the fab and the lab. The cycle time and cost of technology development have become cost-prohibitive, and an alternative solution is required, particularly with the current process complexity of 3D device structures and heterogenous integration schemes.
SEMulator3D® is a 3D semiconductor process modeling platform that can perform fast and accurate 'virtual fabrication' of semiconductor and MEMS devices. SEMulator3D can predictively model any fabrication process applied to any semiconductor design. Starting from a "virtual" silicon wafer, the product performs a series of unit processes like those in the fab to create highly accurate 3D computer models of the predicted structures on wafer. These virtual structures can be generated and analyzed in a fraction of the time and cost of an in-fab experiment and can be used to examine proposed process changes and expected or actual process failures. The product allows engineers to parallel the capabilities of actual fabs, and understand manufacturing issues early in the development process, to reduce time-consuming and costly silicon learning cycles. SEMulator3D is being used by most of the world’s major logic and memory device manufacturers to accelerate their time to market.
Samsung Foundry certified ANSYS multiphysics simulation solutions for its latest multi-die integration™ (MDI) advanced two and a half dimensional/three-dimensional integrated circuit (2.5D/3D-IC) packaging technology. The certification empowers mutual customers to achieve higher performance and lower power within a smaller form factor when designing 2.5/3D-ICs for AI, 5G, automotive, networking and high-performance computing (HPC) applications.
System-in-Package designs are highly complex with multiple dies integrated on an interposer in a 2.5D/3D packaging configuration. Samsung Foundry certifies ANSYS® Icepak® and ANSYS® RedHawk™ family of solutions for power, signal and thermal integrity and reliability analyses. The certification allows for detailed modeling of silicon interposer, through silicon vias, microbumps, high-bandwidth memory, high-speed interfaces and different dies, which is critical for accurately simulating power, signal thermal integrity effects.
zGlue / ChipBuilder 3.0
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Device Manufacturer of the Year
Nepes, one of the top tier advanced packaging service providers, has initiated supply of high-reliability Fan-Out package service to a US based leading wireless chip maker. Fan-Out manufacturing is stabilized for mass production of the advanced package line recently acquired from Deca Technologies.
“High Reliability Fan-out Package,” supplied by nepes, is a high-tech solution with more than 2 times BLR (Board Level Reliability) performance versus standard fan-out technologies by reducing physical stress on chips through sidewall protection structures. It also uses “Adaptive Patterning” technology which can help to reduce die drift, one of the most chronic problems in the fan-out package, resulting in a higher-yield and higher-quality product at a lower cost. Currently, only two companies, nepes included, can mass-produce this advanced package solution.
StratEdge Corporation, founded in 1992, designs, manufactures, and provides assembly services for a complete line of high-performance semiconductor packages operating from DC to 63+ GHz for the high-speed digital, mixed signal, broadband wireless, satellite, point-to-point/multipoint, VSAT, and test and measurement industries. StratEdge offers post-fired ceramic, low cost molded ceramic, and ceramic QFN packages, and specializes in packages for extremely demanding gallium arsenide (GaAs) and gallium nitride (GaN) devices. All packages are lead-free and most meet RoHS and WEEE standards. StratEdge is an ISO 9001:2015 certified facility located in Santee, California, near San Diego.
Heterogeneous integration using system-in-package (SiP) approaches is now recognized as the way forward to enable technologies like artificial intelligence, 5G, edge and cloud computing, electric vehicles (EVs) and advanced driver assist systems (ADAS), wearables and more. All of these require different types of SiP, ranging in density, functionality, and cost. It also requires a spirit of collaboration across the supply chain to achieve. Not only does ASE offer a broad spectrum of SiP solutions, but the company takes an active role as an ecosystem partner to support innovation. In fan-out technologies, ASE offers chip-first eWLB, chip-first M-Series, and also higher cost chip-last. It has demonstrated 2µm l/s on 300mm round panels, and are working on ]even finer features to create a higher productivity interposer replacement.
OmniVision Technologies, Inc.
OmniVision is a leading developer of advanced digital imaging solutions. Our award-winning CMOS imaging technology enables superior image quality in many of today’s consumer and commercial applications, including mobile, automotive, security, IoT/emerging, computing, and medical. We’re on a relentless quest for technology breakthroughs, mostly recently achieving the Guinness World Record for the smallest commercially available image sensor with our medical sensor that reduces invasive procedures and cross-contamination for disposable endoscopic applications. We also launched the automotive industry’s first high resolution sensors with HDR, LFM and cybersecurity, assisting in a safer driving experience with the latest imaging technologies. We are consistently one of the top three global CMOS image sensor manufacturers. As the only image-sensor company that serves every image-sensor market segment worldwide, we cover the entire market at a more comprehensive level than our competitors.
Device Technology of the Year
Co-EMIB (Intel EMIB and Foveros combined)
Intel’s EMIB and Foveros technologies leverage high-density interconnects to enable high bandwidth at low power, with I/O density on par with or better than competitive approaches. The company’s new Co-EMIB technology enables the linkage of even more computing performance and capability together. Co-EMIB allows for the interconnection of two or more Foveros elements with essentially the performance of a single chip. And designers can also connect analog, memory and other tiles with very high bandwidth and at very low power.
3D Integration For HPC & AI, CEA-Leti
The chiplet-on-interposer concept involves integrating a multiplicity of chips on a common Silicon platform unlike the concept of large monolithic systems on chip (SoCs). The active interposer extends this notion by adding smart functions at the interposer level, in particular by integrating CMOS components. The interposer is more than a simple interconnection platform; it becomes the foundation for analog and low power digital and photonic functions and increased 3D communication, especially with network-on-chip architectures. The INTACT proof of concept uses 96-core architecture comprising 6 chiplets (FDSOI 28 nm node) 3D-stacked on an active silicon interposer (CMOS 65 nm node). Advanced 3D Technology: 150,000 chiplet connections using ultra-fine pitch die-to-die interconnect, 14,000 TSVs through interposer. Advanced 3D Architecture: active interposer providing network-on-chip for chiplet-to-chiplet communication in a scalable, configurable, cache coherent system.
TSMC's bumpless System on Integrated Chip (SoIC™) is a 3D chiplet solution that features ultra-high-density-vertical stacking for high performance, low power, and minimum resistance-inductance-capacitance. SoICs are built using front-end 3D processes and can comprise mixed nodes, actives and passives, III-V materials, and even memory. Dies are stacked on an active interposer with or without TSVs using hybrid bonding. This bumpless approach achieves <10µm bond pad pitch between chips. SoICs can eventually achieve sub-micron density, unlike 3D ICs, which only achieve multi-micron density with C4 or micro-bumps. After dicing, SoICs can be integrated via back-end 3D in InFO or CoWoS packages. It is a drop-in replacement for system-on-chip (SoC).
SmartSens - SC132GS (Metis)
The merging of 5G and AI technology is accelerating toward an “intelligent” upgrade. SC132GS – a Voltage Domain global shutter image sensor built on BSI Stacked Pixel Technology – has powerful performance advantages such as high sensitivity, low noise-to-signal ratio, high shutter efficiency (>99.99%), single-frame HDR with improved PRNU performance and self-knee point calibration. What truly distinguishes SC132GS is its broad applicability, such as for facial identification, biological recognition, code scanning, machine vision, 3D imaging and any application that requires a steady flow of complex information. SmartSens meets these demands by integrating additional imaging features directly onto the sensor chip using stacked technology. Practically speaking, this means ultra-high performance in imaging sensitivity and clarity even in non-ideal lighting; low power consumption; and most importantly, the ability to process images at the sensor level.
OmniVision’s OX08A and OX08B Automotive Image Sensors
The first two members of OmniVision’s new image sensor platform offer the automotive industry’s best imaging clarity and range for ADAS and level 3+ autonomous vehicles. They’re the auto industry’s first sensors with 8.3MP, 140dB HDR and LED flicker mitigation (LFM). The high-resolution OX08A features the automotive industry’s leading HDR, while the pin-compatible OX08B adds a new benchmark in LFM performance, enabled by the sensor’s on-chip HALE (HDR and LFM engine) combination algorithm. This advanced functionality is, in turn, enabled by 3D stacking technology.
Previous sensors forced a choice between maximum HDR or LFM, and in lower resolution. The optimal clarity and range offered by this platform, in combination with integrated ASIL-C features, is vital for front-view automotive applications, such as ADAS and level 3+ autonomous vehicles, where the ability to accurately detect people and objects from far away in all lighting conditions is safety-critical.
Engineer of the Year
Dr. Doug Yu, Vice President of Integrated Interconnect and Packaging, TSMC
Research, development, and commercialization of advanced packaging and system integration solutions, System on Integrated Chips (SoICTM) and their derivatives, TSMC’s wafer-level system integration technologies, Chip on Wafer on Substrate (CoWoS®), and Integrated Fan-Out (InFO).
Beth Keser and Steffen Kröhnert, Co-Authors, Advances in Embedded & Fan-out Wafer Level Packaging Technologies
Drs. Keser and Kröhnert are nominated for their work publishing "Advances in Embedded and Fan-Out Wafer Level Packaging Technologies (Wiley - IEEE)."
About the book: Embedded and fan-out wafer level packaging (FO-WLP) technologies have been developed across the industry over the past 15 years and have been in high volume manufacturing for nearly a decade. This book covers the advances that have been made in this new packaging technology and discusses the many benefits it provides to the electronic packaging industry and supply chain. It provides a compact overview of the major types of technologies offered in this field, on what is available, how it is processed, what is driving its development, and the pros and cons.
Bill Chen, Chair of the HIR and Fellow at ASE
Bill Chen, Chair of the HIR and Fellow at ASE, is being nominated for his tireless efforts to bring the Heterogeneous Integration Roadmap (HIR) into reality. He was instrumental throughout the process, and his name is synonymous with this initiative. The HIR initiative has been a significant undertaking for the entire Advanced Packaging and 3D community over the past few years, and its publication in 2019 is a great achievement. The roadmap offers professionals, industry, academia and research institutes a comprehensive, strategic forecast of technology over the next 15 years. The HIR also delivers a 25-year projection for heterogeneous integration of emerging devices and materials with longer research-and-development timelines.
Laura Mirkarimi, VP 3D Portfolio and Technologies, Xperi
Laura Mirkarimi, VP 3D Portfolio and Technologies, Xperi led the team that successfully developed Xperi DBI Ultra, which the same elegant, room-temperature bonding approach as wafer-to-wafer (W2W) DBI, with the added benefit of being both die-to-wafer (D2W) and die-to-die (D2D) processes. It can be used in high volume manufacturing to stack memory, and also integrate that memory with sensors and logic in a 2.5D or 3D system-in-package (SiP).
Annette Teng, Ph.D. CTO of Promex Industries
As CTO of Promex Industries in Santa Clara, Dr. Annette Teng has made key contributions to the company’s packaging technology. Her fundamental knowledge has enabled Promex to provide world-class wafer- and substrate-processing capabilities. She has further developed highly innovative, custom processes to meet customers’ unique requirements. As a strong advocate, sponsor and mentor of Promex interns, Dr. Teng has influenced their success –- either when returning to their studies or in remaining at Promex to make valuable contributions to the engineering team.
Dr. Teng is highly active in the packaging community. She has served as an officer of the Santa Clara Chapter of the IEEE Electronics Packaging Society (EPS), and received the 2018 EPS Regional Contributions Award for Regions 1-6, 7 and 9. With ASE’s Dr. Bill Chen, she co-chaired the Heterogeneous Integration Roadmap (HIR) Working Group on Single-Chip and Multi-Chip Integration and is co-organizing the 3rd annual HIR Symposium.
Equipment Supplier of the Year
Onto Innovation Inc.
Onto Innovation was created in October 2019, out of the merger of two strong companies, Nanometrics and Rudolph Technologies, each with a leading market position and a long legacy of success. The merger creates a true end-to-end supplier for our customers, as Onto Innovation combines global scale with an expanded portfolio of leading-edge technologies that include: Unpatterned wafer quality; 3D metrology spanning chip features from nanometer scale transistors to large die interconnects; macro defect inspection of wafers and packages; metal interconnect composition; factory analytics; and lithography for advanced semiconductor packaging. Onto Innovation is expected to be the fourth largest semiconductor capital equipment supplier by revenue in the U.S. and a top 15 semiconductor equipment company by revenue worldwide. Onto Innovation strives to optimize customers’ critical path of progress by making them smarter, faster and more efficient.
ERS electronic GmbH
For 50 years, ERS has been leveraging their unique expertise to bring new products to the market, starting with the introduction of the first-ever air-cooled chuck, which redefined the industry status quo at the time.
Last year, despite the turbulent industry conditions, we remained at the forefront of thermal management technology by introducing the first-ever Manual Debonding Machine for Panel-level. This development served as a catalyst for the industry’s transition from wafer to panel-level packaging, and has enabled other research facilities to further the development of Advanced Packaging technologies. The customer and market response to the machine proved that the risk was worth taking, and that panel-level is a trend that equipment suppliers should not ignore. To show that we intend to stay a driving force of FO innovation, we are now working on releasing the first-of-its-kind Automatic Panel Debonding Machine, with planned launch at the end of 2020.
SmartView® NT3 Automated Bond Alignment System, EV Group
As the pioneer in wafer bonding, EV Group continuously sets new performance benchmarks in wafer bond alignment for next-gen applications. The SmartView® NT3 face-to-face bond aligner, which is available on EVG’s leading GEMINI® FB XT integrated fusion bonding platform for high-volume manufacturing applications, redefines what is possible in wafer bonding - helping the industry push the envelope in enabling stacked devices with greater density and performance, lower power consumption and smaller footprint.
The SmartView NT3 aligner was developed specifically for fusion and hybrid wafer bonding. It provides sub-50-nm wafer-to-wafer alignment accuracy (a 2-3X improvement) as well as significantly higher throughput compared to the previous generation.
The SmartView NT3 aligner provides unmatched wafer bonding performance and can meet future 3D-IC packaging requirements. Applications include flash memory stacking, 3D SoC, stacked backside illuminated CMOS image sensors and die partitioning.
Materials Supplier of the Year
Brewer Science has been supplying advanced materials to the semiconductor market for over thirty-nine years. For the last fifteen years, Brewer Science has been supplying temporary bonding/debonding materials that cover a wide variety of release methods, including chemical, thermal slide, mechanical, and laser release materials. These products provide the user with increased throughput, performance, and yield rates. Brewer Science’s wafer-level packaging materials enable device manufacturers to reduce the form factor and increase the efficiency of their products and processes. Brewer Science is committed to solving the biggest challenges in the compound semiconductor, 2.5D, 3DIC, and fan-out packaging market spaces.
Released and qualified a new Cu RDL chemical which delivers highest reliability for sub 5µm LS combined with the capability of via filling to enable next generation of Fan Out technology. The chemistry suite can be used in every available tool set, existing or new., fountain or vertical.
The deposited Cu achieves highest Cu purity, lowest impurity level for Sulfur and Chloride which results in no voiding after temperature budget and finally can be used for Cu-Cu bonding, µBump technology and Cu Pillar.
Plan Optik AG
Plan Optik AG is the leading manufacturer of glass wafers when it comes to technology. For more than 40 years, Plan Optik supplies glass materials in sectors such as consumer electronics, automotive, aerospace, chemistry, and pharmaceuticals. Plan Optik’s high-quality wafers are used as essential components for numerous applications in MEMS and Sensor technology. The wafers made of glass, glass-silicon compounds or quartz materials are available in sizes up to 300 mm diameter with application-specific structuring and complex material combinations.
To serve the high demand for glass wafers with fixed specifications more quickly, Plan Optik has founded Wafer Universe to provide off the shelf products. Therefore, every customer can be served with glass wafers that respond to its needs – simple and fast.
Process of the Year
DBI® Ultra, a revolutionary, low temperature die-to-wafer and die-to-die hybrid bonding process, that enables new era of 3D integration that was not possible before. Among a wide range of applications, DBI Ultra makes it possible to manufacture 4-, 8-, 12- and 16-high High Bandwidth Memory stacks while meeting the demanding packaging height and performance requirements for next generation, high-performance computing. By eliminating the need for copper pillars and underfill, DBI Ultra can enable a dramatically thinner stack than conventional approaches. DBI Ultra also allows the stacking of known good die that are the same or different sizes, processed on fine or coarse wafer process technology nodes, or manufactured on the same or different wafer sizes while readily scaling down to 1 um interconnect pitch. DBI Ultra is suitable for 3D stacked memory, such as 3DS DRAM as well as 2.5D and 3D applications requiring the integration of memory with CPUs, GPUs, FPGAs, or SoCs.
Quazi-Zero Die Shift, Brewer Science
Brewer Science has been instrumental in developing materials and processes enabling advancements in temporary carrier technology. This has enabled the creation novel fan-out wafer-level (FO-WLP) packaging requirements targeting 20-µm pitch interconnect for chip-to-chip placement. To achieve this density and to further scale it down, a critical element is ultra-precise die-to-die positioning in the micron range. Advances in temporary bonding materials and carrier systems are required to enable such applications. Recently developed materials have shown that it is possible to transfer ultrathin reconstituted substrates (thickness below 100 µm) between two carrier substrates with minimal to zero die shift.
Cu-Interposer technology, Plan Optik
The progressive miniaturization, increasing integration density and requirements for more powerful signal routing create the need for 3D integration. Interposer technologies for rewiring have been developed for efficient communication with high transmission rates in the 3D chip stack or 3D system package. But: There is no established solution to produce glass interposers at wafer level, which provides all required properties for high-frequency applications. For this reason, Plan Optik has developed a new process to apply copper layer on glass wafers, which is particularly suited for high-frequency applications, like for example 5G broadband transmission, radar and imaging sensors, biosensors or beam steering networks. This process will be used for Plan Optik’s Cu-Interposer which can be produced as a wafers, panels or boards. Further products, manufactured with the mentioned process - like Glass-Circuit-Boards with IPD's - will come soon.
ChipInFlex: Wafer Level Integration Of Thin Silicon Bare Dies Within Flexible Label, CEA-Leti
ChipInFlex is CEA-Leti’s latest development towards the integration of ultra-thin silicon bare dies within a flexible film. Working with silicon wafers help achieve high resolution of integration. Silicon wafers are well-suited for flexible fan-out packaging. ChipInFlex is also the first packaging solution that can perform collective thinning on the wafer. The electrical interconnection is achieved with gold stud-bumps made on bare dies. The process has been successfully validated on an electrical test vehicle. The first step towards a full electronic system in a flexible label has been made.
Dielectric-core-based HAR Thru-Package-Vias forming using 3D-RDL. 3DiS Technology
Integrating all building blocks of an RF Frontend for 5G applications in a small package and enabling optimal interfacing of said package with antenna array or integrating such antennas inside it (AiP) requires advanced 3D system packaging techniques. These include forming interconnects inside the package, multiple height thru-package-vias and backside RDL. 3DiS Technologies developed a low-cost wafer-level process that allows to form such multi-height, high aspect ratio "HAR" TPVs (10:1) simultaneously with 3D-RDL that interconnects 3D stacked dies inside the package. Not only this solution is independent of number of stacked dies and their thicknesses, it enables direct 3D integration inside the package cost-effectively. Technology was demonstrated on 3D-IPD devices and 3D RF SiP with stacked dies inside the package.
YES Vacuum Cure
YES vacuum cure technology supports today’s most advanced MEMS and semiconductor process applications. Whether for complete curing of polyimide in WLP/RDL applications or annealing copper in an advanced semiconductor device, YES’s vacuum cure systems achieve total environmental control to increase yields and extend device performance. Compared to the traditional atmospheric cure, YES’s vacuum cure process offers complete outgassing with no trapped solvents, excellent electrical and thermal performance, superior resistance to warping at high temperatures, particle elimination, temperature uniformity, shorter process time, reduction in nitrogen usage and fast ROI. As dielectric materials have evolved to meet the challenges of WLP and emerging FOWLP applications, the need for a perfect cure has become mission-critical. Consequently, YES’s vacuum cure has become the technology of choice for Fortune 100 companies implementing FOWLP.
Research Institute of the Year
UCLA Center for Heterogeneous Integration and Performance Scaling
UCLA CHIPS is an interdisciplinary university-led consortium composed of industrial partners and consortia, universities and government agencies to holistically address a fundamental re-thinking of IC and system design and manufacture. Starting from the application space, the design environment, and the integration scheme, appropriate new materials and components are being developed. These include energy sources, memory, sensors, passives, electromechanical and medical devices – all of which need to be integrated into these new platforms and application space.
UCLA CHIPS has pioneered the dielet revolution and develops new methodologies and infrastructure for integrating dielets (sometimes also called chiplets) at pitches comparable to on-chip wiring levels, enabling both latencies, bandwidth and energy per bit comparable to monolithic integration, but at the board level.
Fraunhofer Institute for Electronic Nano Systems ENAS, Chemnitz, Germany
Fraunhofer ENAS is an innovative and reliable system and technology partner in the field of smart systems integration by using micro and nano technologies. They develop single components, technologies for their manufacturing as well as system concepts and system integration technologies for various applications and transfers them into production. The institute offers research and development services from idea via design to technology development. As an example we are highlighting the department Micro Materials Center (MMC), working on micro-reliability and nano-reliability. They combine advanced numerical simulation with various experimental methods to validate the models. As leader of a complete work package in European Project EuroPAT-MASIP they developed a fully parameterized model for the FOWLP technology platform, supporting virtual prototyping predicting the thermo-mechanical behavior of the recon wafer throughout the process flow and predict component reliability.
Leti is paving the way to future high-efficiency systems for high-performance computing with its chiplet-on-interposer concept, as well as its wafer-level integration of thin silicon bare dies within a flexible label. Additionally, ongoing activities in 3D VLSI technology have resulted in the achievement of 1µm pitches in wafer-to-wafer and die-to-wafer stacking using hybrid bonding technology. They are also developing ultra-fine pitch 500 nm hybrid bonding technology. In their CoolCube program, they have proved with a test chip that a 500°C thermal budget for the top layers is acceptable. A multi-project wafer has been recently launched for this monolithic 3D IC solution.
Startup of the Year
Sensry GmbH, Dresden, Germany offers high level of flexibility for IoT-Modules, answering the ever-changing customer needs, is key for success in this market. Sensry, established in 2018, has a cooperation with Fraunhofer (development) and Globalfoundries (production). The company is a lean start-up, driving innovation in a highly insecure environment by implementing “Build-Measure-Learn” cycle between Idea, Product and Data. They offer a universal platform for all integrated smart secure sensors. Heart of the second product generation is an SoC developed by Sensry and manufactured by GF in 22nm FDX. The base module hosts the SoC and Passives in FOWLP 3D-SiP with TPV interconnect bus to the package backside. The IoT-Module is then customized by heterogeneous integration on package level allowing their customers fast Time-to-Market. Different to other solutions, the concept allows access to the latest wafer processing and packaging technologies for fast prototyping and ramp also for SMEs with initially small volumes.
FFLICQ is an edge computing startup based in Silicon Valley with offices in Perth, Aberdeen, Chennai and Amsterdam. FLICQ's wireless smart sensors provide the simplest way for companies to monitor their remote assets in real-time. FLICQ's AI-enabled sensors process analytics close to where the data is collected - at the "edge" of the Industrial IoT (IIoT) network. FLICQ's customers use the analytics to extract valuable information about the health of their industrial assets to improve their operating efficiency. Key customer benefits include:
• maintenance-free sensor platform with a multi-year battery life
• low-latency system architecture enabling rapid response to changes in asset health
• cellular-friendly solution requiring no additional infrastructure
FLICQ's integrated sensor solutions are built using system-in-package technology, leveraging low-power designs to deliver the industry's longest battery life and unmatched analytics capability.
Fast-growing mini and micro LED technology startup Rohinni was created when its founders, recognizing the manufacturing and cost challenges inhibiting micro LEDs from entering mainstream use, set out to remove these roadblocks. Rohinni’s technology eliminates cumbersome, costly LED packaging, and allows for the creation of thinner, lighter, brighter and more energy-efficient consumer electronics. To accelerate getting products into the market that use its technology, Rohinni has formed strategic joint ventures with industry leaders in their respective markets.
At CES 2020, Rohinni showed, with leading panel maker BOE, first demos from their JV, BOE Pixey, that will bring the power and brilliance of micro LEDs to mass-market fruition, enabling consumer electronics makers to meet both current and future demand for higher-quality displays. BOE Pixey anticipates that mini and micro LED-based displays utilizing its technology will become available for purchase in the second half of 2020.
Startup SVXR has developed the first fully automated, inline x-ray inspection system for detecting 100% of defects in advanced IC Packages. Inspecting up to 10,000 solder connections per second, the X200 detects random defects and process variations in all types of advanced packages, including 2.5D, stacked die, high-density SiP’s and micro-bump FC. The X200 interfaces to the production line for seamless integration, and is fully SECS/GEM compatible. Operating over 100x faster than existing x-ray systems, the SVXR X200’s unique x-ray inspection technology is not only faster but safer than traditional x-ray inspection for sensitive IC’s, including DRAM and CMOS.
In 2019, SVXR’s X200 tool was released to the market and successfully installed in multiple production sites in Taiwan, Korea, and Japan. By enabling continuous quality monitoring and real-time defect detection, the X200 improves quality, increases yield, reduces costs, and shortens time to market for advanced IC packages.
Winners will be selected by a panel of five judges:
- Jan Vardaman, Techsearch International, Inc.
- Mike Pinelis, Microtech Ventures
- Jean-Christoph Eloy, Yole Développement
- Rozalia Beica, 3D Industry Expert.
The fifth judge is YOU, the 3D InCites Community, via the online ballot. Vote Here
Awards will be presented in a ceremony during the IMAPS Device Packaging Conference in Fountain Hills, AZ (March 2-5, 2020). We are accepting nominations through January 29, 2020.