The IMAPS 2021 program is set to be knowledge-packed, offering materials both in person and on demand, including keynote presentations from top experts, professional development courses, numerous technical sessions and over a dozen posters. Our 3D InCites community members are playing a large role in dispersing this knowledge through their participation as technical track presenters and chairs, panel moderators, in keynotes, special sessions and more! If you haven’t been to an in-person event in a while, now is a good time!
Here are some of the key activities our members are involved in:
Monday, October 11, 2021
Professional Development Courses
8:00 am – 10:00 am
Course A1: System-in-Package (SiP) – System Solutions Through Miniaturization –Instructor: Mark Gerber, ASE US, Inc.
This PDC course will introduce the package platform SiP (System-in-Package) and how some companies are diversifying from SOC (System-on-a-Chip) to leverage heterogeneous silicon integration and package miniaturization to enable system level solutions.
1:00 pm -3:00 pm
Course C1: The Evolution of Flip Chip Package Technology – Instructor: Mark Gerber, ASE US, Inc.
This PDC course will provide a historical overview and background on the evolution of flip chip packaging as well as short market perspective on this platform. Mobile, Infrastructure, Automotive, High Reliability, Medical and High-Performance Network and Computing all rely on Flip Chip technology to enable their silicon solutions.
Tuesday, October 12, 2021
KEYNOTE 2: 10:15 am – 11:00 am
More Moore or More than Moore. An EDA perspective
Over the past 30+ years there‘s been a significant shift in the way commercial electronics have been designed. There are many inflection points that have influenced how consumer electronics and systems products are developed across many vertical markets including transportation, 5G, wireless communications, industrial, medical, and more. This talk will discuss the impact several drivers including Moore‘s Law, as well as advances in the design of semiconductors, systems, and advance packaging.
KT Moore, Cadence Design Systems, Inc., Vice President
Wednesday, October 13, 2021
Technical Sessions
WAFER / HYBRID BONDING
10:45 am – 11:10 am
Prevention of Thinned Wafer Deformation During Thermocompression Bonding Supported by Temporary Bonding Materials
Alice Guerrero, Brewer Science, Inc. (Pieter Bex, Alain Phommahaxay, Eric Beyne, IMEC; Andy Jones, Daojie Dong, Brewer Science, Inc.; Arthur Southard, Brewer Science Taiwan)
PANEL-LEVEL FAN OUT
4:45 pm –5:10pm
Adaptive Patterning Methods and Applications
Ryan Bartling, Deca Technologies Inc.
EVENING KEYNOTE & PANEL
6:45-8:30pm
PANEL: NEXT GENERATION PACKAGES: ARE WE READY?
Moderator: Jan Vardaman, President and Founder of TechSearch International, Inc.
New package options are required to meet the needs of advanced silicon nodes and cost reduction. Adoption of Co-packaged optics is anticipated. The industry requires a health infrastructure to meet future packaging needs including heterogeneous integration and chiplets. Are we ready? What infrastructure issues need to be addressed? This panel discusses challenges in meeting the needs of next generation packaging and provides insight into potential solutions.
Thursday, October 14, 2021
KEYNOTE 6: 9:00 am – 9:45 am (Virtual Presentation)
A NEW ERA FOR GLASS IN MICROELECTRONICS PACKAGING
For glass, it would be inappropriate to speak of a new material in microelectronics. It is considered one of the oldest man-made materials and is also regularly used in electronic packaging already. However, if we look at the fundamental material properties of glass, the only question that really arises is: why isn’t it used in a greater number of applications? The answer to the question lies in the widespread believe that glass is difficult or uneconomical to process on a microscale.
This presentation will describe how recent developments in the field of laser-induced deep etching are helping to enable novelle packages and bring glass to a new era in micro-electronics.
Roman Ostholt, LPKF Laser & Electronics AG, Managing Director
12:15 pm – 3:00 pm
Special Invited Session: Heterogenous Integration Roadmap
Session Chair: Bill Chen, ASE
Topics: Medical Health & Wearable, MEMS & Sensor Integration, Security, Supply Chain
Exhibitor Booths
ASE Group 202, 204
Finetech 208
QP Technologies 109
StratEdge Corporation 409
On Demand Presentations
A-Manufacturing Optimization
Track Chairs: Dongshun Bai, Brewer Science and Suresh Jayaraman, Amkor
TPM1 – Design, Modeling & System Simulation
Memory Packaging Challenges for a Growing Market — Knowlton Olmstead, Richard Strode, Curtis Zwenger, Amkor Technology
Design Constraints and Scale Down Evolution in Advanced Semiconductor Packages — Byong Jin Kim1, SangHyeon Lee1, JaeBeom Shim1, Nam-Hee Cho2, JinYoung Khim1
Amkor Technology Korea, Inc., Incheon, Korea, Materials Science and Engineering of Inha University, Incheon, Korea
B – Wafer Level/Panel Level (Advanced RDL)
WAM2 – Panel-level Fan out
Alternative FCBGA Package Solution Evaluation: High-speed Design Optimization and Electrical Characterization of FOBGA – Hung-Hsiang (Marco) Cheng, Advanced Semiconductor Engineering (ASE) (Cheng-Yu Wu, Hung-Chun Kuo, Chen-Chao Wang, Guo-Cheng Liao, Yun-Hsiang Tien, Yi-Chuan Ding)
WPM2 – WLCSP (Fan In and Advance Material
Effect of Novel SAC-Bi Solder Joints on Electromigration Reliability for Wafer Level Chip Scale Packages – Min-Yan (Brian) Tsai, Advanced Semiconductor Engineering (ASE) (Yung-Sheng Lin, Chin-Li Kao, Shan-Bo Wang, Ting-Chun Lin, Yun-Ching Hung)
THAM2 – Module Warpage / Plating Solution Contamination Mitigation
The Pivotal Role of Uniformity of Electrolytic Deposition Processes to Improve the Reliability of Advanced Packaging – Ralf Schmidt, Atotech
D – Advanced Packaging (Flip Chip/2.5D/3D/Optical)
WAM4 – Heterogeneous Integration and 3D
Thermal and Stress Analysis of 3D SiP Module for 5G Application – Hung-Hsien Huang, ASE Group (Wei-Hong Lai, Bing-Yuan Huang, Dao-Long Chen, David Tarng, CP Hung)
THAM4 – Interconnect
High Density Package Design Platform and Assembly Design Kit – Chih-Yi Huang, Advanced Semiconductor Engineering Inc. (ASE)
E – Advanced Process & Materials (Enabling Technologies)
TPM5 – Advanced Substrate Materials
Cu Crystal Structures in Plated Microvias. Recrystallisation & a Means to Identify Joints at Risk of Premature Failure – Roger Massey, Atotech Deutschland GmbH (Tobias Bernhard, Killian Klaeden, Sebastian Zarwell, Stefan Kempa, Edith Steinheauser, Frank Bruning)
Emergence of glass solutions for 5G and Heterogeneous Integration – Shelby Nelson, Mosaic Microsystems (Aric Shorey, David Levy, Paul Ballentine)
