Remember when device node scaling was the semiconductor superstar, and advanced packaging was the back-up singer? At the 15th Annual IMAPS Device Packaging Conference, held March 5-7, 2019, in Fountain Hills, AZ, it became clear how rapidly that hierarchy has shifted.
From the keynotes to the panel discussion, to the Global Business Council session, speakers portrayed heterogenous integration (HI) as the shining star to enable a greener, smarter, healthier, and more connected world.
Why? Because more compute power alone does not solve all the challenges of today’s varied market drivers, which include artificial intelligence (AI), machine learning (ML), 5G, internet of things (IoT), and blockchain for automotive, industrial and personal applications. These require the heterogeneous integration of disparate technologies including microelectromechanical systems (MEMS), sensors, RF, analog and digital processing, and more.
With this in mind, the IMAPS committee designed this year’s program to highlight sensor integration, business, and technical drivers for an autonomous world, packaging for power semiconductors, and advanced packaging for the 4th industrial revolution.
A Tale of Two Theories: Feynman and Moore
Benedetto Vigna, ST Microelectronics, discussed the past, present, and future of sensor technology, highlighting pivotal moments that have driven the industry. For example, the commercial CMOS image sensor market exploded once Nokia included it in a cell phone. After that, Motorola started pushing the MEMS microphone. He attributed Nintendo’s WII for the consumerization of MEMS in 2006.
Vigna also compared the theories of Gordon Moore and Nobel Physics laureate, Richard Feynman. Moore is well known for his work in device node scaling, the results of which is the famous Moore’s Law. What is less known is Feynman’s revelation spoken in 1985 during a presentation at the Gakushuin University in Tokyo on the computing machines of the future:
“Another direction of improvement (of computing power) is to make physical machines three dimensional instead of all on a surface of a chip (2D). That can be done in stages instead of all at once – you can have several layers and then add many more layers as time goes on.”
As Vigna explained it, Moore’s Law is more related to front-end technology, and Feynman’s theory is related to assembly and packaging. When it came time to choose the best way to integrate sensors, Vigna noted that there was no standard platform and that each company used its own technology. While there are a few examples of integrating MEMS using system-on-chip (SoC) – a Moore’s Law approach – most have been integrated as a system-in-package (SiP. MEMS technology is not about the SoC, but more about SiP, he said. Therefore, it’s time to stop talking about the More than Moore Roadmap, and start talking about the Feynman Roadmap.
Innovations for an Autonomous World
Vigna also touched on the pervasiveness of automotive sensors needed to achieve level five autonomy, including vision cameras, LiDAR, radar, and ultrasound, as well as motion, environmental sensors, and microphones. He noted that level five autonomy in vehicles is taking longer than we expected to be commercialized, and he doesn’t expect we will see it before 2040 in all cities, except in restricted areas.
Alternatively, Veer Dhandapani, NXP said he thinks full autonomy is coming faster than we expected (2025) because of the megatrends driving change. Comparing it to the way smartphones changed the way we think and do things; autonomous driving will change our lives in ways we haven’t thought about. He evangelized about autonomous vehicles being the key to achieving zero emissions, zero congestion, and zero accidents. It’s all about saving lives, going green, and enjoying the ride, he said.
What’s more, the semiconductor industry stands to profit handsomely from autonomous vehicles. “Safe and secure mobility is more than tripling the semi value per car,” noted Dhandapani.
While he noted that with Waymo full autonomy is here, Dhandapani said there are still challenges to address, such as how to handle the estimated 20 terabytes of raw sensor data being generated by 2025. Most notable is his concern for power generation, and how to increase processing performance without an over-proportional increase in power. This will require both technology innovation and infrastructure with zone-based architecture.
Welcome to the Advanced Packaging Party!
After years of downplaying the importance of packaging in its hot pursuit of Moore’s Law, Intel is finally all in on HI. It was interesting to hear keynoter Sriram Srinivasan deliver the same messages we’ve been talking about for the past 10 years like they were a brand-new concept.
Srinivasan posed the concept of scaling packaging features to keep up with Moore’s Law and deliver a smaller package footprint for compact systems. He said Intel supports HI to deliver high functionality at optimal cost, as well as higher quality and reliability.
While I was hoping to hear details on Foveros technology, which is Intel’s new 3D face-to-face chiplet stacking approach for heterogeneous integration, he spent more time revisiting embedded multi-die interconnect bridge (EMIB), the company’s alternative to fan-out wafer level packaging that was introduced in 2016. What he did say about Foveros is that its development was driven by a need for integration complexity and power savings/management. It offers improved thermal performance, as 3D stacked chips have higher thermal resistance than 2D silicon.
Srinivasan concluded by noting that next-generation multi-chip packages must scale simultaneously along multiple directions to meet future I/O, power delivery and test demands. Platform-level co-design is required for optimal design points.
Heterogeneous Integration: Why Now?
Srinivasan’s talk segued nicely into Tuesday evening’s manel on heterogeneous integration (no, that’s not a typo: it’s what I call a panel comprised entirely of men, except for the moderator, Jan Vardaman, Techsearch International Inc.)
- Rajendra (Raj) Pendse, Facebook Reality Labs
- Nokibul Islam, JCET Group
- Dan Oh, Samsung Electronics
- Mike Kelly, Amkor Technology
- Mark Gerber, ASE
- Sriram Srinivasan, Intel Corporation
Discussing the drivers for HI, opinions varied from high-performance computing to imaging and display technology, to automotive applications. Samsung’s Dan Oh’s response was the most succinct. “HI is coming because of the cost of shrink,” he said.” Process costs are high, IP designs are expensive. The only way to avoid this and come to market (without needing) two years of development time is if you can use an alternative.”
The panelist agreed that OSATS, foundries, device makers and system houses all have an important role to play. “It’s not so much about one role being more important than the other,” noted Pendse. “the role of the system house is foundational. It starts by architecting the product and partitioning it. The most important role is for the system house to architect the teams.”
Islam noted that while the system house comes up with the requirements, he’d like to see would like to see pro-active codesign and collaboration from the beginning to solve issues and make everyone successful.
Comments from the Peanut Gallery
Two of the most interesting points made came not from the panelists, but two of the attendees who posed questions that weren’t really addressed by the panelists’ response.
Citing his 15 years of experience in the front-end combined with 15 years in the back-end, Christo Bojkov, TriQuint (talked about the challenges posed by integrating different technologies with different design rules. When you compact things together by shrinking elements in the back-end to meet the front end, reliability issues ensue, he said. What’s missing from this discussion then, is the perspective of the materials suppliers, because materials considerations – for example, what will replace copper or how to handle thermal budget – needs to be discussed.
Andrew Hollowell, Sandia National Labs, noted that HI calls for a multidisciplinary skill set. He asked the panelists what their companies are doing to encourage the next generation of engineers to acquire this skillset.
Maybe they didn’t quite understand the question, because rather than address it, each panelist seemed to revert to prepared responses.
ASE’s Gerber assured Hollowell that the company has “an army of engineers” working on HI. Islam said the number #1 criteria for HI success is design, and that they work in close collaboration with system houses. Oh and Srinivasan each said Samsung and Intel have all the skills in-house, and Pendse said Facebook’s open compute platform encourages collaboration.
It’s the Power, Stupid!
Saving “the best for last”, Dan Oh, Samsung, and Raj Pendse, Facebook, presented the final two keynotes on advanced packaging innovations for the fourth industrial revolution and for AR/VR hardware, respectively.
As is often the case with day three of a conference, many of the overarching points that I mentioned earlier were reiterated by these speakers. So let me wrap up this blog with a few key points they made.
Oh noted that advanced system integration is a crucial part of the computing revolution, and requires both hardware and software. SiP is key to integration, and 3D SiP will be the path forward.
For the 5G mobile platform, we need a smaller form factor, higher bandwidth, and thermal improvements. Fan-out SiP is Samsung’s answer because the application processor and memory can be placed side by side, for better thermal performance than fan-out package-on-package.
For AR/VR devices, Pendse said taking cues from the human system provides the most efficient solutions. There is a three order of magnitude power gap between the human brain and the smartphone. To truly enrich the user experience, we have to create ways to improve power efficiency. He believes that AR/VR could take 3D packaging mainstream.
Talk about burying the lead…. Until next time! ~ FvT