Dev Gupta Disrupts the Fan-out Panel at IMAPS DPC, You Won’t Believe What Else Happened!
Here we go again! One thing is for sure, there is never a dull moment at the IMAPS Device Packaging Conference panel sessions. (Remember the year of Alphabet Soup?) Maybe it’s because they take place AFTER everyone’s had a few drinks, but this year was especially lively and entertaining. There was humor, there was drama, AND there was a really good story being told at the fan-out panel discussion at IMAPS DPC 2017, which took place March 8-10, 2017 in Fountain Hills, AZ. Really, if you were here and decided to skip it, you may have missed out on the best part of the conference.
It started out just like any other panel discussion. Jerome Azemar of Yole Développement assembled an impressive line-up of panelists representing the fan-out wafer level packaging (FOWLP) value chain:
- Rich Rice, ASE Global, Sr. VP Business Development
- Islam Salama, Intel, Director: Pathfinding Department, Substrate and Packaging Technology Development
- Infineon, Johannes Lodermeyer, Wafer Level Technology
- Vinayak Pandey, Product and Technology Marketing Director
After being introduced one at a time, each panelist took a few minutes (or 20 in the case of STATS ChipPAC’s Vinayak Pandey) to talk about his company’s position on FOWLP. From them we learned:
- ASE is more than dabbling in fan-out technologies. They’ve invested significantly in such FOWLP flavors as fan-out system-in-package (FOSiP); fan-out package-on-package (FOPoP), its version of integrated Fan-out (InFO); and fan-out chip-on-substrate (FOCoS), which, as a replacement for 2.5D interposers, reaches 2µm l/s and three redistribution (RDL) layers. Rice reported 27K FOCoS wafers shipped in 2017.
- Intel believes in both the future of scaling and packaging. According to Salama, data is going to be the next disrupter which requires changes in both the hierarchy and composition of the network. This change will drive both Si and packaging technologies. Extending Moore’s Law requires scaling the package. He views packaging as an integral part of system performance. He said fan-out packages will not compete but will co-exist as they each have pros and cons vis-à-vis cost and technologies. As an IDM, the plan is to have captive in-house assembly processes. Salama is partial to a chips-last fan-out approach to avoid yield loss.
- Infineon’s been in the FOWLP business since 2001 when it developed embedded wafer level ball grid array (eWLB) technology. They licensed the technology to ASE, STATS ChipPAC and Nanium in 2008, and introduced it into automotive products in 2012. Lodermeyer explained the main reason for implementing eWLB in automotive applications was its frequency behavior.
- A new law has been established. Pandey’s Law refers to Vinayak Pandey’s personal goal of doubling the number of eWLB units shipped by STATS ChipPAC every three years. Currently, the number is at 1.4B units. He says the path to accomplishing this will involve using eWLB to package everything from single die to multiple dies, MEMS, and more in 2.5D, 3D PoP, and SiP solutions.
- Amidst all the skepticism surrounding the viability of fan-out panel level packaging (FOPLP), both ASE and STATS ChipPAC have it on their roadmaps. According to Rice, ASE has made a significant investment in Deca Technologies to develop large panel processes for its FOWLP technology, which is currently being produced on 300mm round panels. “There are lots of opinions about FOPLP —is this possible or worthwhile to do?” said Rice. “IF ASE didn’t believe it was, they wouldn’t have invested. It’s a viable technology and Deca has some pretty good ideas.” (I’ll talk more about the FOWLP controversy in an upcoming post.)
During the Q&A was when things got lively. It started when Dev Gupta chimed in from the audience that coreless substrate flip chip performs better at a lower cost than FOWLP. While his point was recognized by the panel as technically valid, Azemar explained that it wasn’t an apples-to-apple comparison, as it used a different value chain than FOWLP, and was off topic for the panel. But Gupta dug in with both heels, commandeered a microphone, and wouldn’t let go. What ensued was an unintelligible shouting match between him and Pandey, who was doing his best to respond to Gupta’s rant despite being interrupted repeatedly. For a good 10 minutes, Jerome heroically tried to redirect the discussion to give others a chance to pose questions, but it wasn’t until Gupta’s microphone was retrieved and he left the room that order was restored.
ASE’s John Hunt saved the day (and the discussion) by fielding a question about the differences between chips last and chips first, even though he wasn’t a panelist. He explained that all process flow variations — chips first, die down, chips last, die up —use the same equipment, can achieve the exact same density, and have the same RDL structure. There are other reasons to choose one methodology vs. another. For example, it’s difficult to integrate passives in a chips-first, die-up approach. Chips first mean the die is committed before the RDL patterning is done, so it is more susceptible to yield loss due to RDL defects. With chips last, the RDL patterning is done before anything is molded, so yields are higher.
Still there, are reasons why one method is chosen over the other; each has pros and cons, explained Hunt. eWLB, a chips-first approach, is manufactured in higher volumes simply because it was the first in production. Chips first is a fab-based approach that relies on wafer processing capabilities. OSAT expertise lends itself to a chips-last approach.
Despite the skirmish, the panel turned out to be an informative and lively session, and may just go down in history as the most talked-about event of IMAPS DPC 2017.