The Great Miniaturization … SEMI/MEPTEC Conference Nov 10 & 11

After 50 years of following Moore’s Law and reaping major benefits with every feature size reduction, the economics of transistor scaling are now no longer universally applicable. Only designs that can be sold in extremely high volumes are likely to pay back the enormous up-front investment needed to get to production in a timely fashion.

Most companies found – or will find – that, instead of scaling transistors, system scaling is more economical for serving their markets profitably. Customers want smaller, smarter and of course lower priced system with longer battery life and honestly don’t care how suppliers meet these requirements. They’ll never look “under the hood” to check if their latest devices use the smallest feature size transistors to get the job done. They trust us to offer a good solution. It’s totally up to the semiconductor supply chain how we scale systems to make them smaller, smarter, lower power consuming and, at the same time, reduce our cost – to continue offering with every product generation more for less money.

Several decades ago hybrids and modules partially succeeded, and then multi-die packages ( package-on-package (PoP) and system-in-package (SiP)) succeeded widely by integrating multiple dies in an IC package and enabling a few hundred die-to-die interconnects. However they offer relatively low performance per Watt and limited bandwidth between dies. Interposer-based (2.5D) and vertically stacked, TSV-interconnected thinned dies (3D ICs) were developed and have already succeeded in less cost-sensitive applications, especially where bandwidth between CPUs/GPUs and memory cubes is paramount. However, for very cost sensitive applications, like mobile devices and IoT edge nodes, we didn’t have a compelling packaging solution — until our packaging experts took the production-proven, single-die fan-out wafer-level processing technology (FO WLP) and enhanced it significantly, to allow multiple dies per IC package. In addition, just in case processing and molding hundreds of multi-die ICs simultaneously on a 12” wafer would still turn out to be too costly for some high-volume applications, our experts are developing panel-level processing, to spread the manufacturing cost of every batch across thousands of multi-die ICs.

Sorry about this lengthy introduction to outline the background for this conference and substantiate its importance. As more and more of the IC value creation is shifting to the manufacturing back-end, it is great to see how IC packaging experts are transforming their own companies and their supply chains from providers of customer-specific solutions to innovators of widely-applicable, customizable and cost-effective IC packaging technologies.

SEMI, our industry’s largest and most powerful organization, representing material suppliers, equipment vendors and semiconductor manufacturers, joined forces with MEPTEC (MicroElectronics Packaging & Test Engineering Council) to organize and manage a series of presentations and set up an exhibit floor for this 2-day conference.

A widely-known IC packaging expert, Professor Rao Tummala from Georgia Tech, gave the keynote on Tuesday morning. He contrasted the many benefits of system scaling versus the diminishing returns the traditional transistor scaling offers and explained how his Package Research Center (PRC) works with IC vendors and many key players in the IC packaging supply chain. Among other key points, Prof. Tummala showed, what he considers are the fundamentals of system scaling (Figure 1).

Meptec1

Like in many previous presentations, Prof. Tummala recommended the benefits of glass as an interposer substrate – and especially as robust and low-cost panel-level material (see comparison table in my previous blog about GIT 2015) and highlighted that glass is perfect for the ubiquitous RF applications and can serve very well in high growth opportunities, like automotive and industrial IoT edge nodes, because it can stand high temperatures and is mechanically as well as chemically very resistant.

He explained that the many years of R&D experience with glass at PRC, the high-growth potential of automotive electronics and the many automotive companies residing or expanding in the southeastern USA, have motivated Georgia Tech to focus a major part of their R & D efforts and partnership activities on this segment.

After academia gave a longer-range view of IC packaging developments, industry representatives took over.

Amkor’s Prasad Dhond presented how many automotive applications (e.g. power train, instrument cluster, infotainment, body & chassis, EV power electronics, sensors and actuators for safety and driver-less navigation) are now deploying ICs. To meet this segments stringent zero-defect requirements, Amkor has been certified for manufacturing of automotive products. Amkor’s partnership with J-Devices, a proven Japanese IC supplier to the quality-conscious Japanese car industry, further strengthens Amkor’s position in automotive.

Larry Zu from Sarcina Technology, gave us a very technical view of current and future ASIC and multi-die packaging. He showed how die-package-PCB impedance mismatch can degrade performance. He also explained what kind of challenges need to be considered in IC packaging, to meet PAM 2 (25 Gbps) and PAM 4 (56 Gbps) SerDes transmission speeds.

Ou Li from ASE focused her presentation on how IC packages contribute to system integration and -scaling and talked about ASE’s SiP and system-in-module (SiM) capabilities and how they meet IC packaging challenges. Like other conference speakers, she emphasized the importance of die-package-system Co-design, and why the impact of insertion loss and other material characteristics need to be modeled accurately, to provide accurate and current data for accurate simulations and cost-effective system scaling. Last, but not least, Li pointed out that assembly-houses are, within the supply chain, very well positioned to become value-added system integrators.

MEptec2

Right after lunch and interesting discussions on the exhibit floor, Dr. Joan Vrtis, CTO of Multek, talked about enabling a connected world. I fully agree with her prediction that IoT will make our ecosystem smarter and bring a lot of changes to our customers’ markets and our own industry. I also found her slide  (Figure 2) that describes typical reactions to the need for change within a company, very fitting. As “trouble maker” in some of my previous roles (maybe even in my current role …), I found (find…) that pushing for timely changes to adapt to new market needs, starts often with comments #1 and #2 and typically ends with #3.

After Dr. Vrtis, somewhat philosophical presentation, the next speaker turned to medical applications. Andy Kelly, from Cactus Semiconductor talked about how miniaturization will make it easier to implant electronic devices or position them very close to the body and aid patients unobtrusively. While ensuring safe and reliable operation are of course very important for these devices, it surprised me that for implants both accuracy of signal capture as well as data transmission speed are not at all demanding.

In the last session of the first day we learned about how to save power and how to harvest energy within a device.

Debbie Senesky, a Stanford professor, demonstrated her in-depth knowledge about Gallium Nitride and its many applications in low-power sensors for very high temperature environments.

Globalfoundries’ Tim Dry, filling in for Jamie Schaeffer, presented their IoT market focus and outlined Globalfoundries’ fully depleted SOI platform: 22FDXTM. He stated that its cost-competitive with 28 nm bulkCMOS, offers performance like 16/14 nm FinFETs at much lower power, can operate down to 0.4 Volts, simplifies back-biasing and is well-suited for RF applications. He also showed the broad support 22FDX now gets from design services, EDA & IP vendors, industry organizations and listed several suppliers for blank FD-SOI wafers.

– I found that the highlight of the day, in regards to innovation power, was clearly Douglas Tham’s energy harvesting presentation. He is Co-founder and CTO of Silicium Energy and explained why and how his company is going to replace batteries in wirelessly connected devices with their energy harvesting technology. It converts heat (e.g. body heat) into electricity and will make re-charging or replacing batteries a thing of the past for many low-power applications.

An evening reception and informative discussions with the exhibitors ended the first day. Read Part 2 here.  ~ Herb

Herb Reiter

After more than 20 years in technical and business roles at semiconductor and EDA companies,…

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