More than 25 years ago, Professor Rao Tummala founded Georgia Tech’s Package Research Center. However, his vision that advanced IC packaging technology would “graduate” soon and play a major role in the semiconductor industry didn’t come true for a long time.
About a decade ago, the first generation of advanced packaging technologies — package-on-package (PoP) and system-in-package (SiP) — finally was broadly rolled out and became the enablers and differentiators for outsourced semiconductor assembly and test service (OSATS) providers winning high-volume orders in the smart-phone market and from mobile device makers in general. A second generation, the performance-focused, interposer-based multi-die ICs joined this race at the beginning of this decade. Just a few years ago, the third generation of multi-die ICs became available. OSATs had developed, based on the proven and very cost-effective single-die wafer-level processing (WLP) flow, multi-die fan-out WLP technology. It offers high performance AND can meet the cost- and package height constraints in mobile devices very well. I expect that multi-die FOWLP production volumes in 2016 will surprise most multi-die integration skeptics and make generations two and three very compelling packaging solution for a broad range of applications.
In early November, Georgia Tech’s 5th Interposer Workshop attracted 180 packaging and manufacturing experts from 13 different countries. They presented their latest advancements in multi-die IC packaging technology, materials, and new IC packaging concepts, manufacturing flows as well as IC- and package design tools.
On the first day, Wednesday afternoon, Nov 4, several well-known key players presented. Intel’s Bob Sankman described their embedded multi-die interconnect bridge (EMIB) as well as it’s technical and cost advantages for applications requiring high-bandwidth. Dave McCann from GlobalFoundries outlined which market requirements they focus on, talked about stitched silicon interposers (currently up to 29×40 mm) and Globalfoundries’ multi-die packaging cooperation with partners.
TSMC’s Doug Yu compared TSMC’s proven interposer-based CoWoS concept and the newer, low-cost Integrated Fan Out (InFO) wafer-level technology that’s targeted at very thin mobile devices. Xilinx’ Suresh Ramalingam presented the SLIT solution, another TSV-less wafer-level packaging technology for multi-die solutions jointly developed with SPIL. Amkor’s Rick Reed also confirmed the customers’ demand for much lower cost multi-die integration. He presented SLIM and SWIFT as Amkor’s answers to market requirements for TSV-less, low-cost wafer-level packaging.
Last, but certainly not least, AMD’s Bryan Black described the challenges he had to overcome when developing Fiji, a super high-performance graphics solution, together with ASE and Hynix. Black proudly announced that gaming enthusiasts can now buy a complete system, called Fury, for about only $600 at Amazon and enjoy the blazing performance of AMD’s GPU, paired with 4GB of HBM memory, communicating over a 1000 bit wide bus, clocked at 1 GHz.
This impressive first day clearly showed that more interposer-based solutions are demonstrating compelling performance benefits and power savings, not only in high-end computing- and networking applications, but also for graphics enthusiasts, a slice of the consumer market. Equally important, all the new TSV-less, wafer-level packaging solutions (InFO, SLIM, SLIT, SWIFT) described above, combine interposer and substrate into one low-cost wafer- or panel-level carrier that will allow injection molding of many multi-die ICs simultaneously. This very low-cost solution is targeted at cost-sensitive, high-volume mobile applications.
Professor Tummala’s introduction on Thursday morning included a number of key points:
- Shrinking below 14nm doesn’t offer cost reductions any more, except for extremely high volume applications.
- After 50 years of transistor scaling, we need to focus on system scaling and shrink package substrates, PCBs, passive components, heat sinks, chip-to-chip and board-to-board interconnections, batteries, and other components to achieve smaller, lighter, smarter, lower power and of course lower cost systems. Simply shrinking system geometries will already result in higher performance at lower power dissipation (= longer battery life and/or lower operating cost) as well as better reliability.
- While transistor features shrank from 1960 to 2010 by 1000x, I/O pitches are only 5x lower. Interposers and the wide die-to-die busses they enable (e.g. 1000 bits) help to close this enormous gap and offer a path to practically unlimited bandwidth.
- The characteristics of interposer material is very important for a design’s success. Like in previous year, Prof. Tummala highlighted the versatility and cost advantages of glass interposers, as they are getting ready for production ramp-up. See the table below:
Prof. Tummala and later speakers from glass interposer suppliers (Asahi, Corning, Schott,…) emphasized that previous challenges, like via drilling (now up to 5000 per second) and interconnect trace adhesion have been solved very well. Also, today thermal coefficient of expansion (CTE) of glass interposers can be matched to silicon, package substrate or board, to improve reliability.
Considering that worldwide about 80 million cars are being manufactured per year, the electronics content per car is likely to reach $ 10k in the coming years. As a number of car manufacturers operate factories in the South-East US, Prof. Tummala also described Georgia Tech’s many strengths as automotive development partners.
All speakers during Thursday’s and Friday’s sessions outlined their commitment to manufacturing of interposer-based and/or wafer/panel-level multi-die packaging. They showed tables with impressive manufacturing capabilities and material characteristics (thickness, line/space pitches, via diameters, throughput, loss tangent,…) but, as I expected, nobody talked about automating the flow of this data into the multi-die IC design flows at customers. This is needed to empower System- and IC designers to plan their designs and choose the most appropriate manufacturing solution(s). Considering that the materials- and equipment vendors have already invested billions of dollars in R & D and CapEx to get ready for manufacturing of advanced multi-die ICs, it’s high time to broaden the cooperation between EDA tools developers and manufacturing experts to make planning, implementing and verifying of multi-die ICs easier and faster. Prof. Tummala and his conference co-chairs, Prof. Subu Iyer from UCLA and Qualcomm’s Matt Nowak, are of course aware of this bottleneck and once again scheduled a Design Tools session as part of this year’s conference. I got about 20 minutes on Friday morning to encourage the assembled 100+ manufacturing experts why and how they need to intensify the cooperation with EDA Design Tools vendors.
About 20 years ago, in my role at Synopsys, I worked with TSMC on their first reference flows and a Process Design Kit (PDK). It specified available building blocks (TSMC libraries), set ground rules how to best utilize their processes’ capabilities and published design hand-off guide lines. Their first and many following PDKs have accelerated IC design, minimized communication errors, have always provided up-to-date information, minimized time to market and risk. All these PDK benefits are key contributors to relatively high margins at TSMC and other foundries.
Manufacturing advanced IC packaging solutions, if it isn’t already, is bound to get equally challenging as wafer fabrication, therefor the need for PDK equivalents, called Assembly Design Kits (ADKs) will grow and will eventually offer the same benefits as listed above for PDKs. Accurate modeling of readily available packaging building blocks will become more important to reducing tooling cost. Equally important, detailed material characteristics and equipment capabilities will further increase to help high-volume customers optimize their custom packages. Cooperation between IC packaging experts, EDA partners and large IC vendors will be needed to make ADKs reduce development cost, time-to-market and help multi-die IC designers to walk the fine line between costly over-design and risky under-design.
To encourage closer cooperation between materials- and IC packaging experts on one side and IC design services and EDA tools vendors on the other, I pointed out in my presentation that I have organized a 4 hour multi-die modeling and design tutorial, to be held in Redwood City, CA, on December 15, in context with the 12th 3D ASIP conference. Both multi-die IC suppliers and their customers will benefit significantly from the expert presentations and a 200+ page Multi-die IC Design Guide available to attendees.
The next speaker at the EDA session, Georgia Tech’s Prof. Swaminathan, gave a perfect example of multi-die design challenges with his presentation: “Challenges and opportunities in power delivery”. Multiple dies in a package demand more supply current, versus single-die ICs, impact each other through the supply lines and through electrical, thermal and magnetic interference. Prof. Swaminathan outlined already developed solutions and encouraged interested companies to join the ongoing development program to further expand these capabilities and broaden the range of applications.
The next presentation from Zuken’s Humair Mandavia highlighted the complexity of today’s system- and IC design. Using an actual joint Denso & Zuken multi-die design project, Mandavia showed how Zuken’s multi-die design flow, together with ANSYS tools, enabled Denso to complete a complex design in about one year. That’s a relatively short period of time, considering that it took Xilinx 6 years and many prototypes to get to a reliable quad-FPGA design. Bryan Black stated that his team at AMD took 8 years and many iterations to finish their super high-performance graphics solution. Both projects were done before good multi-die IC design tools were available and required many time-consuming trial-and-error loops until the developers could narrow down their focus to the most promising alternative.
Refined EDA tools and jointly developed Assembly Design Kits will cut design times and cost for integrating multiple dies into a single IC package by an order of magnitude. This will enable many more users to benefit from performance, low power, small form factor, modularity, time-to-market savings and cost benefits of multi-die packaging solutions. ~ Herb