3D InCites’ Guest Blogger, Paul Werbaneth shares his impressions and takeaways from November’s 3D Test Workshop. Welcome back Paul, we’ve missed you! I haven’t been to another conference or workshop in recent memory at which I’ve smiled as much as I did at the 3D IC Test Workshop (Nov 8-9, 2012) held at the Disneyland Hotel, in conjunction with the IEEE International Test Conference. goofyThe staff at the check-in counter, for example, must be trained to extract a smile from you soon as you walk up to the desk. Oh, wait, my smile started when I saw a life-sized Goofy making friends with awestruck tots right there in the lobby before I even hit the desk; no, wait, my smile started even before then, when my wife caught sight of Mickey and Minnie Mouse statues near the bubbling fountain under the portico and asked to be photographed with them right then and there. Say “Cheese!” My happy rounds continued the morning of the 9th (I was only able to participate in the workshop one day) when, looking around the venue in search of breakfast and the registration table, I realized what a small world it is indeed as I bumped into Professor Ken Rose, Rensselaer Polytechnic Institute, my old friend from the SEMI / IEEE Advanced Semiconductor Manufacturing Conference.  Smiles from us both as Ken led me in the direction of my badge, my coffee and the workshop.  Thank you Ken! My primary role at the workshop was serving as a panel member for the 3D Buzz: Hype versus Reality Editor’s Panel Discussion, serving at the behest of Françoise von Trapp, Queen of 3D, 3D InCites, and Sr. Technology Writer, Impress Labs. Thank you Françoise, for inviting me to participate, and thank you also for running such a lively panel discussion.  I was honored to be in such distinguished company, and happy that we had fun with the discussion. My other role at 3D IC Test?  Writing this summary for you of my impressions and take-away thoughts from the workshop. But first a word from the musician Tom Waits, from the 1999 album Mule Variations, specifically, lyrics from the song “What’s He Building in There?” just to take you into my head regarding this 3D IC Test Workshop: “What’s he building in there? What the hell is he building in there? He has subscriptions to those magazines… He never waves when he goes by…  He’s hiding something from the rest of us… He’s all to himself… What’s he building in there?” Remind you of any test engineers you know?  What’s he testing in there?  What the hell is he testing in there? For me, with my background and interests, while listening to the workshop presentations on 3D IC testing, my focus was not on the how of testing so much as it was on the what. What’s he testing in there?  It was something like this: For fabrication processes and process node descriptions, we heard that ST-Ericsson is using a CEA/LETI/STM 65nm process node via-middle process with 8:1 aspect ratio Through Silicon Vias (TSVs) arrayed on a 40µm pitch.  The imec “Vesuvius” 2.5D test vehicle came up in the Cascade Microtech talk, but process details were light here compared to the detailed discussion of TSV/Micro-bump testing on array pitches of 40µm and 30µm. I would imagine the 65nm process is already a high-yielding wafer fabrication process, just as I imagine the TSMC 90nm process mentioned in the National Taiwan University paper must also be, so both processes would seem good vehicles for understanding the yield impacts of introducing TSV / 3D IC architectures into trailing-edge, bread-and-butter wafer fabrication nodes. On the other hand, FormFactor/MicroProbe, along with Altera, are working right at the bleeding edge of wafer fabrication technology, using the 20nm process node TSMC 2.5D / 3D IC process for their work on understanding 40µm pitch grid-array probing.  I imagine there must be so many confounding factors gating device yields at 20nm that it’s only electrical test results, not good die out, that’s of interest to them this year. In terms of what, 3D IC Test Workshop needs a pretty big tent to fit all flavors-of-interest of 3D vehicles discussed:  For ST-Ericsson the 3D demonstrators of choice were heterogeneous digital-on-analog, memory-on-processor, and processor-on-processor applications; for FormFactor/MicroProbe/Altera it was heterogeneous FPGA on interposer (naturally); Cascade Microtech spoke about homogeneous wide I/O memory and heterogeneous memory-on-processor being of interest; for Cadence Design Systems it was heterogeneous / multiple tower stacks on interposers;  and for Mentor Graphics, heterogeneous memory-on-processor-on-interposer. I always appreciate when device makers talk about device yield — which they are mostly loath to do for good reason — so I was happy to hear ST-Ericsson report that while added process steps in the TSV process flow should result in some yield hit just from the defect potential resulting from die stacking at TSV formation (it certainly increases costs), no yield losses were observed, albeit with the caveat that the data are limited. “Encouraging results,” said ST-Ericsson about their pre-packaged yields, but maybe some yield loss should be expected when 3D IC devices are packaged. And, finally, what more could you want out of a 3D IC testing workshop’s whats but the what of practical testing tips?  For example, the tip about the need to test TSVs pre-bond, promoted by ST-Ericsson in their Keynote Address, and echoed by many others along the way. Tips for assessing 3D IC production costs versus the markets in which the 3D products are targeting deployment came from FormFactor/MicroProbe, which has determined probe card cost for fine-pitch 40µm TSV structures may be too much for anything but high-end >$100 ASP products; and from Cascade Microtech, where the cost of 3D TSV probe heads for fine pitch (40µm and 30µm) applications are still being determined. Ken Rose’s advice was to make sure and get the design-for-manufacture (DFM) right as you work on the design for test (DFT). “If you can’t reasonably manufacture a part using a TSV process then you are behind the curve,” explained Rose. “Does a $2800 wafer work with a $190 TSV process when the TSV process itself is potential depressing yield as it adds cost?” Sage advice also came from Cadence Design: higher compound yields are achieved by stacking smaller known-good-dies first before stacking anything onto the largest, most expensive die you have. You have the right to know what he’s testing in there (thank you again Tom Waits), and I hope with this summary of what I heard he’s testing in there you’ll wonder no longer. From Petaluma, CA, thanks for reading. ~ PFW

Paul Werbaneth

Paul Werbaneth is a long-time Contributing Editor at 3D InCites. Since entering the semiconductor industry…

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