Latest Posts - Page 2
Delft University of Technology and imec Introduce 3D-COSTAR to Optimize Test Flows of 3D Stacked Integrated Circuits
Delft University of Technology (TU Delft) and nanoelectronics research center imec, introduced 3D-COSTAR, a new test flow cost modeling tool...
Interview with imec’s Ludo Deferm: Packaging Design Kits and Debond Solutions
For me, SEMICON West involves a careful balance of attending sessions, keynotes and panels, combined with one-on-one interviews with thought...
Silicon Photonics: the Next Killer App for 3D ICs? and more from the R&D Community
First it was going to be memory stacks, then it was Wide I/O DRAM on Memory, and now, as commercialization... EV Group Celebrates Strong Growth and New Manufacturing Process Solutions at SEMICON West 2013
Demand For Flexible, High-Volume Manufacturing Solutions in 3D-IC/Advanced Packaging, MEMS, Power Device and Compound Semiconductor Markets Drive Growth SEMICON WEST,...
Sum of Minds – imec Makes the Unexpected Happen
In her opening remarks at the 2013 imec International Technology Forum (ITF), held Monday, July 8, 2013, Karen Savala, SEMI,...
ASMC 2013 and 3D IC: Time to Volume, Time to Via
What is today’s biggest threat to continued growth in the semiconductor industry? Subramani Kengeri, Vice President, Advanced Technology Architecture, GLOBALFOUNDRIES,...
European 3D TSV Summit: But Wait, There’s More!
Day Two of the European 3D TSV Summit dawned bright and clear, with such a spectacular view of the nearby... European 3D TSV Summit: Focus on Cost of Ownership
Now that the “technology bricks” for building 2.5D devices and 3D ICs have been essentially qualified, the focus has turned...
3D ICs News in Brief – Jan. 19-29
While there is still a lot to report about the European TSV Summit, I wanted to catch everyone up on...
