One by one, it looks like to-do items are being checked off the list of TSV adoption limitations for 3D ICs, and it seems that collaborative efforts are making the most progress in achieving desired consequences. For example, we’ve been hearing the cry for design tools for quite some time, and yesterday Javelin Design Automation, in cooperation with IMEC and Qualcomm, announced a breakthrough with its Pathfinder tool for design exploration and optimization of 3D stacked ICs (3D SIC).

According to a joint statement, The team developed a detailed 3D flow to determine accurate performance/power/cost estimates for a 3D stack. The flow was then validated by using it in a smart phone application. The results demonstrated how using TSVs as the method of interconnect allows for a decrease in power, thereby allowing for an increase of bus-width between microprocessor and memory.

Pol Marchal, principal scientist of IMEC who worked on the project, explained some of the ramifications of this work to me. “The PathFinding tool brings 3D technology one step closer to adoptation as it helps to assess the cost/benefits of 3D technology in the early phases of design.” he said. IDMs hesitate to adopt 3D, he explained, because they don’t understand system benefits. Additionally, he said if they do have ideas, they have no way to determine how their system-level decisions might complicate physical designs. By creating a prototype with this tool, the system design team can obtain valuable insights in the power/performance/cost trade-offs for various 3D integration scenarios. One example of comparing these trade-offs was with IMEC’s studies in 3D WLP vs. 3D SIC.

Additionally, integration and packaging teams can benefit from reviewing the prototypes to address and perhaps eliminate manufacturing challenges 3D stacks pose down the line. For example, Marchal explained, can the envisioned 3D stack be packaged? Can the dissipated power be removed from the stack? Is the stack mechanically reliable? Relying on a prototype rather than a spreadsheet allows for practical and focused discussion, which in turn allows for easier evaluation of alternative integration schemes. “As 3D system-level decisions have such impact on final cost, we believe that physical design prototyping will become an essential step in the 3D design flow,” said Marchal, adding that in addition to the path finding tool, obvious follow-ons will include design authoring and verification tools for 3D place and route, layout, layout versus schematic check / design rule check, extraction, etc.

What’s most interesting to me in this latest achievement, is the demonstration once again of the power of collaboration to bring ideas closer to fruition. In cases like this, everybody wins. Javelin gets to be the first out of the gate with a marketable tool that’s been validated by two reputable organizations. IMEC has access to a tool that could very well catapult forward further research in 3D integration. Qualcomm gets to reap the benefits as an early adopter of 3D technologies in their products. I’d say that’s a pretty good start to the week. – F.v.T.

Francoise von Trapp

They call me the “Queen of 3D” because I have been following the course of…

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