Today’s 3D day kicked off with a very broad and thorough state-of-the-technology report from imec’s perspective, presented by Paul Marchal. I covered imec’s progress a few weeks ago in an interview with Eric Beyne, after the research center’s technology forum event. In his keynote, Marchal drills down into some detail, complete with application examples.
Marchal’s overall message was 3D integration as a cornerstone for heterogeneous integration, zeroing in on enabling sensor integration into mobile devices. He explained that conventional scaling will not allow us to add functionality while maintaining the same dollar cost, because the amount of functionality per dollar has increased. Because of the level of functionality that sensors can bring to smartphones and tablets, the user-perceived value of sensors now exceeds that of transistors.Therefore, integrating sensors into these devices is the next step to provide diverse functionality into a compact form factor.
An example of the benefits of heterogenous integration can be seen in mixing MEMS and CMOS to achieve “the ultimate form-factor,” notes Marchal. By using TSVs in a chip-scale packaging approach, the periphery of the outside of the package can be eliminated for significant area savings. Additionally, a silicon or glass interposer allows for the elimination of the PCB. How is 3D integration cost beneficial in this instance? Marchal explained that the additional cost of using TSVs is offset by the additional number of die you can get on the wafer. “Using smaller die sizes gets you a 2X reduction in cost using TSVs.” he said. He also gave examples of 3D integration used for CMOS image sensor technology, combining analog and digital applications, and integrating embedded passives on the substrate.
Marchal went on to discuss particular work in 3D technologies at imec, and identified the institute’s process of record as TSV middle, with TSVs measuring 5×50µm; and for interposers measuring 10×100µm.
“I do not see any big issue anymore in TSV processing,” he noted, citing good control in etch processes, void-fill, and high reliability. “TSVs are not hampering adoption of 3D technology.” However, as TSVs scale to smaller nodes, the copper pumping issue that has been solved at the moment may become an ongoing concern. “We’re doing detailed assessments to manage this,” he said.
Although great progress has been made with thin wafer handling, Marchal says it’s still a problem requiring further improvement. For example, there are issues with TSV-induced cracks, and a support system for shipping ultrathin wafers doesn’t exist. “Testing thin wafers has some practical problems that need to be resolved,” he added. “It’s not impossible, but needs further work.”
Then Marchal posed the million dollar question: “Since everything is great and solutions are available, why are people not jumping up and down to adopt this?” he asked. The answer: Cost. “For many, it’s still too expensive and they want us to look for ways to bring down costs.” He said the TSVs themselves make of 40% of cost of 3D. That cost is related to processing, expensive tools, and the keep out zone (KOZ) on active die which sacrifices valuable real estate. SInce the KOZ scales linearly with the size of the TSVs, making the TSV diameters smaller can reduce the cost. New process TSV technology developments are ongoing to decrease cost or increase AR of TSV while not incurring cost penalty. The next target AR, says Marchal, is 17:1 3µm diameter and 50µm deep.
On the topic of thermal challenges, Marchal said they are application-dependent. For example in the mobile space, the heat sources are small and the density is low, so the thermal issues are minor. With higher power densities, the heat sources are bigger, and so are the thermal issues. But in these cases the cost of the interposer needed to solve this can be absorbed.
Co-opitimization of chip and package is also key (he called it chip/package interaction or CPI), and Marchal said the trend is to co-optimize mechanically. He talked about a “quick and dirty” design flow that provides an early assessment of timing/power/area/and cost of 3D product ideas that helps with early chip planning.
Lastly, he noted that testing is underestimated, and that imec has put a strong focus on design for test for 3D, and cost effective and damage-free probing for known good die (KGD) testing. Marchal also said that imec is actively pursuing microbump testing, .
Overall, Marchal was optimistic about 3D technologies, calling it “a very appealing technology.” Basically, the benefits are worth figuring out how to reduce cost, fit it to your application, and make it optimal for CPI.
There’s much more to come on the 3D day at IWLPC, particularly about the panel. But first, I’m off to moderate a 3D panel at the 3D Test Workshop in Anaheim. Never a dull moment in the world of 3D! ~ F.v.T.