In her opening remarks at the 2013 imec International Technology Forum (ITF), held Monday, July 8, 2013, Karen Savala, SEMI, said it best – this event, preceding SEMICON West, is a great way to set our mindset for the rest of the week. I couldn’t agree more. What I have always found most exciting about imec is that its researchers get to play in the idea sandbox and not only envision what is possible, but make it possible. As imec CEO and president, Luc van den hove, noted in his presentation, “Sum of Minds,” imec performs the “funneling” process, narrowing the options so industry partners can focus on the most likely options, which helps reduced cost of R&D. imec’s goal is to remain two to four generations ahead of what’s being manufactured today.
To create these possibilities to begin with, imec has created a unique infrastructure, bringing talent across disciplines, countries and cultures to create innovation. “If you bring together people with truly complementary skills, you can make the unexpected happen,” explains Van den hove.This is what he means by “Sum of Minds”, which was the focus of this year’s ITF
To demonstrate the power of bringing together multiple disciplines, Van den hove focused on three topics that are important projects for the research institute – cell sorter, scaling memory and logic beyond 10nm, and plastic displays.
imec’s cell sorter project is the “holy grail for early cancer detection,” says Van den hove, which brings together CMOS, life science technologies, prototyping qualification and fabrication, image sensor and vision systems, and MEMS technology, to build a system that detects and sorts circulating tumor cells from healthy red and white blood cells in order to detect cancer at early stages. Current systems are large and bulky, and rely on manual processes. imec’s innovation integrates CMOS image sensors, microfluidics, ASIC circuits, FPGAs, high speed data and cell biology that “allows us to bring sophisticated analysis to compact tools.” Van den hove says using silicon technology allows for 1000 channels to function in parallel on one chip.
To zoom in on process advancements, Van den hove talked bout scaling memory and logic beyond 10nm. Along with lithography nodes, double patterning and EUV, he talked about 3D stacking a major trend to address this challenge. “For 8 to 10 years we’ve been pioneering this technology,” he said, which allows for multiple die to be stacked into highly integrated systems including analog, digital, and chips from different technology generations using through silicon vias (TSVs). Understanding these processes and architectures requires a combination of different skills.
But even 3D integration will have its limitations, and with the explosion of high bandwidth needs, may realize sufficiently high bandwidth. However, Van den hove says integrating silicon photonics components using 3D integration and interposer technology will allow those needs to be met.
While most of the remaining presentations throughout the ITF focused on such topics as the transition to 450mm wafers, advanced lithography processes for further scaling, finFETS and alternative materials, and emerging memory technologies (including the hybrid memory cube), Paul Marchal, who presented on Design for Future Technologies, talked at length about 3D integration and its “tremendous potential for a number of applications”, particularly heterogeneous integration and 3D interposer stacking. “The crux of this technology is becoming available today. TSVs are out there. We’ve been working on how to do high aspect ratio vias in a reliable way.” he said, adding that the technology has achieved intrinsic reliability; backside thinning and processing has been worked out, design tools are available, and the first applications are being realized. As is common knowledge, the remaining hurdles are yield and cost. “It’s important to understand where yield and cost issue comes from,” noted Marchal. “There’s the intrinsic cost of the technology, but its the cost related to assembly yield that is important to manage.” In an optimal case, he explained, you can slice logic, combine four die in a perfect way on an interposer, and if it works and tests out, you can achieve significant cost savings. One area of imec development he touched on is a a novel e-chuck to improve assembly yield that has great potential for high OSAT flow. He also talked about mechanical modeling to design 3D chip stacks.
Lastly, he talked about the advantages of integrating silicon photonics to meet the 1000x bandwidth challenge, in which every chip will need to be able to read 1000x more data than it does today. Si photonics has a higher data rate in a smaller footprint, whats more, he said it will truly be enabled by 3D integration technology.