A long-time evangelist of 3D integration technologies, Herb Reiter puts more than 20 years of experiences in technical and business roles at semiconductor and EDA companies to work, providing a holistic perspective and insight on how to bring 3D integration to the masses.
Like many other industry conferences, the Electronic Design Process Symposium (EDPS 2020) had to go virtual. Not only did it keep our audience safe but allowed us to attract almost 200 registrants worldwide. Thanks to sponsorships from – ANSYS, Cadence, CEDA, Intel, Mentor – A Siemens Business, and Synopsys –...
During in-person and on-line meetings, I often discuss with friends the impressive progress our industry has made in the last 50 years following Moore’s Law. In 1981, when I joined the industry, on-die feature sizes were 3 microns (= 3000 nm). Today, some IC designers already rely on 3 nm...
If you bought a new car recently, you must have noticed that it warns you if one of its functions needs your attention. It even alerts the factory if repairs or major adjustments are needed. Wouldn’t it be nice to have similar capabilities for our bodies that will call for...
Just like most other events that attract a large number of people, TSMC 2020 events were held online too. While I missed the many friends I normally meet at TSMC events, I was able to follow the powerful messages from TSMC, its Open Innovation Platform (OIP) partners, and satisfied customers...
About 70% of the U.S. Gross Domestic Product (GDP) is driven by consumer demand. What consumers are looking for is influenced by, for example, fashion trends, product innovations, environmental forces, and personal interests. Regarding personal interests: Sales of electronic components at Fry’s are poor, Radio Shack stores even vanished completely....
Several decades ago, Asia began its quest to be a reliable and cost-effective IC packaging, assembly, and test partner for low complexity ICs. Since then, Asia has proven itself as the world’s dominant wafer manufacturer and developer of process technologies, down to smallest feature sizes. On August 4, 2020, I...
In the early days of ASIC technology, only logic library elements and basic I/Os with up to 10s of transistors were available for customizing gate arrays and/or logic functions in standard cell chips. And then, “megacells” (a.k.a. Functional Blocks, Semiconductor IP Blocks), comprised of 100s, even 1000s, and more transistors...
In a recent MEPTEC / iMAPS webinar, Jan Vardaman, President, and Founder of TechSearch International presented growth drivers for advanced packaging and related technology innovations to meet market demand. Unlike in previous years, when she had to spend part of her MEPTEC presentation explaining what the term “advanced packaging” means and...
About 50 years ago, I started my career as a system-level designer, focused on an interface card for the Siemens T 1000. It was the first electronic teletype, destined to ship in extremely high volumes all over the world. When Siemens ramped up production, they invited me to the factory...
In engineering school, I learned that different laws of physics apply when the widely used electricity with 50/60 Hertz gets into the Gigahertz or even Terahertz range. In the decades since, I have managed to keep a safe distance to this challenging world of radio frequencies (RF) needed for transmitting...
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