Wafer and panel-level packaging (WLP/PLP) offers technical and business advantages, compared to traditional IC packages. These cost-effective packaging solutions attracted more than 800 industry experts to the International Wafer Level Packaging Conference (IWLPC 2018) in San Jose’s DoubleTree Hotel at the end of October. In case you were wondering, a multi-die WLP design, created with the tools... »
At this year’s International Wafer-level Packaging Conference, almost 1000 semiconductor experts from all parts of the supply chain gathered at the DoubleTree Hotel in San Jose from October 23 to 25. Among them were also several electronic design automation (EDA) experts who discussed how to streamline die-package-board co-design. They explained how EDA tools enable higher performance per Watt a... »
As I prepared to attend TSMC’s OIP 2018 Forum on October 3, 2018 two emails from TSMC caught my attention. They conveyed the news that TSMC just lowered the entry barrier for SoC design significantly by announcing the OIP Cloud Alliance. This is the latest addition to their four Open Innovation Platform Alliances for EDA, IP, Design Services and Value Chain Aggregators. Having promoted Barcelona... »
The message remains consistent: following Moore’s Law is no longer economical for most IC designs. A major part of the IC value creation is moving from the die to the IC package. Now advanced packaging technologies and materials enable combining multiple dies with heterogeneous functions as well as high-quality passives into one package. This integration increases performance, while significantl... »
SEMICON West (San Francisco, July 10 to 12) confirmed that our industry’s rapid growth will continue. Machine learning (ML) and artificial intelligence (AI) will be the core technologies for a wide range of new applications. Applying AI to win in new and diverse markets – like autonomous cars, medical equipment, military systems, factory automation and a broad range of consumer products – wi... »
This year’s Design Automation Conference (DAC 2018) was held at Moscone West, San Francisco, CA. On three levels, about 175 exhibitors showed their capabilities and discussed market needs. Our industry’s focus on artificial intelligence (AI) and machine learning (ML) solutions were clearly obvious, and I suspect, attracted more young people and a fairly large number of new exhibitors to DAC th... »
May 1st is a holiday in many countries, but not in the U.S. and not for TSMC. A very professional TSMC team and many of its Open Innovation partners demonstrated recent accomplishments to a gathering of more than 2000 attendees at the 2018 TSMC Technology Symposium at the Santa Clara Convention Center. TSMC’s strategy to listen to market needs, analyze how best to meet the requirements and act a... »
On Monday, April 16, 2018, SEMI, the industry association representing the global electronics manufacturing supply chain, and the Electronic System Design (ESD) Alliance, representing the design community, announced a strategic partnership. On Tuesday I had a very informative conference call with Bettina Weiss, VP Business Development at SEMI and Bob Smith, Executive Director, the ESD Alliance to ... »
If you drive a late model car, you may be impressed by the many sensors that capture engine conditions, tire pressure, etc. and report to you. Many cars even call the factory if they need preventive maintenance. Wouldn’t it be great if we could one day show the same preventive tender loving care (TLC) to our own bodies, as our cars enjoy today – instead of experiencing emergency room visits â€... »
Part 1 of my 3D ASIP blog covered the five keynotes presented at 3D ASIP 2017. Part 2 focuses on more than 20 informative presentations, where focused experts gave an in-depth view of new and/or improved technologies for 3DIC-related advanced packaging. Before we address these, allow me a one-sentence recap of Part 1’s key message: We no longer have one major application, like mainframes, PCs, a... »
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