On my annual trek around the ECTC Technology Corner, I’m always on the look-out for something new to write about. This year, it quickly became clear by the number of exhibitors displaying their product samples, that one of my blogs would be an update on fan-out panel-level packaging.

For the past few years, fan-out panel-level packaging (FOPLP) has been in hot debate: is it needed? Does it REALLY offer cost savings over fan-out panel level approaches? Who’s doing it? Is the infrastructure in place for it? When will we see volume production? What will be the first application? Here’s what the PLP experts at Deca, ASE, and Nepes are saying.

When Panel-level Packaging Volumes Come, Deca and ASE will be Ready

Deca had both 300mm reconstituted wafers and a 600 x 600 reconstituted panel on display in its booth at the ECTC technology corner to demonstrate the company’s M-Series™ fan-out technology featuring Adaptive Patterning™. Adams explained what I was looking at (Figure 1). One of the wafers demonstrated pick-an-placed die with the redistribution layer (RDL).  The other 300mm wafer and the panel showed a completely populated and processes wafer, including the RDL and Cu bumps.

Figure 1: Comparison M-Series 300mm round panels, and 600 x 600 square panel.

“It’s hard to believe it (PLP) is real. The only reason it’s not in HVM is that demand isn’t there,” said Adams. When it comes, though, Deca and ASE, which licenses M-Series, will be ready. According to ASE’s Rich Rice, the company is building a facility dedicated to M-Series PLP production.  He says a fully balanced PLP run will produce the device equivalent of 50,000 round wafers. The tools for the facility have been selected and the company is working out the kinks in the processes to determine equipment and process capability. “Full integration still needs work,” he said. “We are watching the market closely and waiting for the demand for HVM.”

Nepes Fabs Out AI Chip

Figure 2: Masayuki Oe and Jay Kim of Nepes with the fingerprint sensor PLP. Note that unlike the M-Series panel, it is divided into 9 quadrants.

Nepes, which licenses reconstituted chip package (RCP) technology, the first FOWLP developed by Freescale before it was acquired by NXP also had PLP on display (Figure 2). As it happens, Jay Kim, General Director and SVP of Nepes’ semiconductor business unit, who was attending the company’s booth at ECTC, authored a chapter in Advances in Embedded and Fan-out Wafer Level Packaging Technologies, the Wiley book I recently reviewed.

According to Kim, the company got an early start in PLP development mainly by leveraging its large-panel liquid crystal display (LCD) experience combined with capabilities in FOWLP. They have demonstrated it in mass production for fingerprint sensor applications. However, Kim noted they have discontinued that line due to a drop in the volume of that application. The purpose of the display is to demonstrate the company’s capabilities. Kim said larger packages benefit from PLP because it uses the area up to 85% more efficiently than round, explained Kim.

The big news for Nepes at ECTC 2019 wasn’t so much about PLP, but about its new neuromorphic artificial intelligence chip, they designed for production at a Korean foundry. It leverages the company’s WLP capabilities, stacking four chips in a package utilizing both fan-out and 3D stacking approaches.

Designing chip architectures doesn’t usually fall under the realm of an outsourced semiconductor assembly and test service (OSAT) provider. Kim explained that Nepes calls itself an “advanced packaging foundry focused on wafer level packaging. We’re different from the big guys,” he explained.

Automatic Handling of Panel-level Packaging Substrates

If you’re wondering how tools will handle panel-level packaging substrates, check out this video sent to me by Hiroyuki Shida, Shin-Etsu Polymer. It demonstrates the automatic handling of PLP in a Class 1 cleanroom for high volume manufacturing (HVM). According to Shida, this video was shot under the assumption of an equipment front-end module (EFEM), and represents the collaborative efforts of TDK, which provided the load port, DAIHEN, which provided the robot, and Shin-Etsu Polymer, which provided the FOUP.

JOINT Consortium with Hitachi Chemical

Figure 3: Hitachi Chemical’s version of PLP.

Nobody was available to speak with me when I stopped by the Hitachi Chemical booth, which was also displaying a FOPLP sample (Figure 3). But I grabbed a couple of photos, and by reading the fine print, here’s what I found out.

Hitachi Chemical is part of the JOINT consortium, which stands for Jisso Open Innovation of Tops. The goal of the consortium is to bring together JISSO materials and equipment supplier members to solve remaining PLP challenges. Other members include Lintec, Uyemura, TOWA, NAAMICs, SMIC, Fuji, SCREEN, Canon, Unimicron, AGC, TOK, Disco, Toray, JSR Corp., Mitsui Kinzoku, and Mitsui Chemicals.

The consortium’s achievements, a panel-die-first, fan-out, system-in-package (SiP) with 1µm l/s feature sizes, was showcased at the Hitachi Chemical booth.

Essentially, the evidence of PLP on display on the exhibit floor demonstrates that several companies are anticipating a market for PLP volume production. All we need now are the orders. Bring ‘em on! ~ FvT

Francoise von Trapp

They call me the “Queen of 3D” because I have been following the course of…

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